View MB90653A_1170708.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds07-13607-3e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16l mb90650a series mb90652a/653a/p653a/654a/f654a n description the mb90650a series are 16-bit microcontrollers designed for high speed real-time processing in consumer product applications such as controlling celluar phones, cd-roms, or vtrs. based on the f 2 mc *1 -16l cpu core, an f 2 mc-16l is used as the cpu. this cpu includes high-level language-support instructions and robust task switching instructions, and additional addressing modes. in order to reduce the consumption current, dual- clock (main/sub) is used. furthermore, low consumption power supply is achieved by using stop mode, sleep mode, watch mode, pseudo-watch mode, cpu intermittent operation mode. microcontrollers in this series have built-in peripheral resources including 10-bit a/d converter, 8-bit d/a converter, uart, 8/16-bit ppg, 8/16-bit up/down counter/timer, i 2 c interface *2 , 8/16-bit i/o timer (input capture, output compare, and 16-bit free-run timer). *1:f 2 mc stands for fujitsu flexible microcontroller. *2:purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. n features f 2 mc-16l cpu ? minimum execution time: 62.5 ns/4 mhz oscillation (uses pll clock multiplication) maximum multiplier = 4 ? instruction set optimized for controller applications object code compatibility with f 2 mc-16(h) (continued) n pac k ag e 100-pin plastic lqfp (fpt-100p-m05) 100-pin plastic qfp (fpt-100p-m06)
2 mb90650a series (continued) wide range of data types (bit, byte, word, and long word) improved instruction cycles provide increased speed additional addressing modes: 23 modes high code efficiency access methods (bank access, linear pointer) high precision operations are enhanced by use of a 32-bit accumulator extended intelligent i/o service (access area extended to 64 kbytes) maximum memory space: 16 mbytes ? enhanced high level language (c) and multitasking support instructions use of a system stack pointer enhanced pointer indirect instructions barrel shift instructions ? improved execution speed: four byte instruction queue ? powerful interrupt function ? automatic data transfer function that does not use instruction (extended i 2 os)
3 mb90650a series n product lineup notes: ? mb90v650a device is assured only when operate with the tools, under the condition of power supply voltage: 2.7 v to 3.3 v, operating temparature: 0 c to 70 c and operating frequency: 1.5 mhz to 8mhz ? for more information about each package, see seciton package dimensions. mb90652a mb90p653a mb90v650a mb90654a mb90f654a classification mask rom product otprom product for evaluation mask rom product flash product rom size 64 kbytes 128 kbytes 256 kbytes ram size 3 kbytes 5 kbytes 8 kbytes power supply voltage 2.2 v to 3.6 v 2.7 v to 5.5 v 2.2 v to 3.6 v 2.4 v to 3.6 v cpu functions the number of instructions: 340 instruction bit length: 8/16 bits instruction length: 1 to 7 bytes data bit length: 1/4/8/16/32 bits minimum execution time: 62.5 ns/4 mhz (pll multiplier = 4) interrupt processing time: 1.0 m s/16 mhz (minimum) por ts i/o ports (n-channel open-drain): 4 i/o ports (cmos): 75 (input pull-up resistors available: 24/ can be set as n-channel open-drain: 8) to t a l : 7 9 a/d converter analog inputs : 8 channels 10-bit resolution conversion time : minimum 6.13 m s/16 mhz analog inputs: 8 channels 10-bit resolution conversion time : minimum 12.25 m s/8 mhz analog inputs : 8 channels 10-bit resolution conversion time : minimum 6.13 m s/16 mhz d/a converter 2 channels (independent), 8-bit resolution, r-2r type 8/16-bit up/down counter/timer 16 bits 1 channel/8 bits 2 channels selectable includes reload and compare functions. i 2 c interface 1 channel master mode/slave mode available uart 1 channel clock synchronous communication clock asynchronous communication i/o extended serial interface 8 bits 2 channels lsb-first or msb-first operation selecable 8/16-bit ppg 8 bits 2 channels/16 bits 1 channel selectable 16-bit i/o timer 1 channel (input capture 2 channels, output compare 4 channels, and free-run timer 1 channel) dtp/external interrupt 8 inputs timer functions timebase timer (18-bit)/watchdog timer (18-bit)/watch timer (15-bit) dtmf generator supports every itu-t (ccitt) tone for output (internal 16 mhz shall be used for dtmf generator). low-power consumption modes cpu intermittent operation mode, sub clock mode, stop mode, sleep mode, watch mode, pseudo-watch mode pll function selectable multiplier: 1/2/3/4 (set a multiplier that does not exceed the assured operation frequency range.) other v pp is shared with the md2 pin (for eprom programming) package fpt-100p-m05, fpt-100p-m06 pga-256c-a02 fpt-100p-m05, fpt-100p-m06 MB90653A item part number
4 mb90650a series n pin assignment 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 rst pa1/out1 pa0/out0 p97/in1 p96/in0 p95/zin1 p94/bin1 p93/ain1/irq7 p92/zin0 p91/bin0 p90/ain0/irq6 p67/ppg11 p66/ppg10 p65/ckot p64/ppg01 p63/ppg00 p62/sck2 p61/sot2 p60/sin2 dtmf p86/out3 p85/irq5 p84/irq4 p83/irq3 p82/irq2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p22/a18 p23/a19 p24/a20 p25/a21 p26/a22 p27/a23 p30/ale p31/rd v ss p32/wrl p33/wrh p34/hrq p35/hak p36/rdy p37/clk p40/sin0 p41/sot0 p42/sck0 p43/sin1 p44/sot1 v cc 2 p45/sck1 p46/adtg p47 p70/sda p71/scl p72 dvrh dv ss p73/da00 p74/da01 av cc avrh avrl av ss p50/an0 p51/an1 p52/an2 p53/an3 v ss p54/an4 p55/an5 p56/an6 p57/an7 p80/irq0 p81/irq1 md0 md1 md2 test p21/a17 p20/a16 p17/ad15 p16/ad14 p15/ad13 p14/ad12 p13/ad11 p12/ad10 p11/ad09 p10/ad08 p07/ad07 p06/ad06 p05/ad05 p04/ad04 p03/ad03 p02/ad02 p01/ad01 p00/ad00 v cc 1 x1 x0 v ss x0a x1a pa2/out2 (top view) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (fpt-100p-m05)
5 mb90650a series 1 p20 / a16 2 p21 / a17 3 p22 / a18 4 p23 / a19 5 p24 / a20 6 p25 / a21 7 p26 / a22 8 p27 / a23 9 p30 / ale 10 p31 / rd 11 v ss 12 p32 / wrl 13 p33 / wrh 14 p34 / hrq 15 p35 / hak 16 p36 / rdy 17 p37 / clk 18 p40 / sin0 19 p41 / sot0 20 p42 / sck0 21 p43 / sin1 22 p44 / sot1 23 v cc 2 24 p45 / sck1 25 p46 / adtg 26 p47 27 p70 / sda 28 p71 / scl 29 p72 30 dvrh x0a x1a pa2 / out2 rst pa1 / out1 pa0 / out0 p97 / in1 p96 / in0 p95 / zin1 p94 / bin1 p93 / ain1 / irq7 p92 / zin0 p91 / bin0 p90 / ain0 / irq6 p67 / ppg11 p66 / ppg10 p65 / ckot p64 / ppg01 p63 / ppg00 p62 / sck2 p61 / sot2 p60 / sin2 dtmf p86 / out3 p85 / irq5 p84 / irq4 p83 / irq3 p82 / irq2 test md2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 dv ss 32 p73 / da00 33 p74 / da01 34 av cc 35 avrh 36 avrl 37 av ss 38 p50 / an0 39 p51 / an1 40 p52 / an2 41 p53 / an3 42 v ss 43 p54 / an4 44 p55 / an5 45 p56 / an6 46 p57 / an7 47 p80 / irq0 48 p81 / irq1 49 md0 50 md1 p17 / ad15 p16 / ad14 p15 / ad13 p14 / ad12 p13 / ad11 p12 / ad10 p11 / ad09 p10 / ad08 p07 / ad07 p06 / ad06 p05 / ad05 p04 / ad04 p03 / ad03 p02 / ad02 p01 / ad01 p00 / ad00 v cc 1 x1 x0 v ss 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 (top view) (fpt-100p-m06)
6 mb90650a series n pin description (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 80 82 x0 a crystal oscillator pin 81 83 x1 a crystal oscillator pin 77 79 x1a b crystal oscillatort pins (32 khz) 78 80 x0a b crystal oscillatort pins (32 khz) 47 to 49 49 to 51 md0 to md2 d operating mode selection pins connect directly to v cc or v ss . 50 52 test d test input pin this pin must always be fixed to h. 75 77 rst c reset input pin 83 to 90 85 to 92 p00 to p07 e (stbc) general-purpose i/o ports pull-up resistors can be set (rd07 to rd00 = 1) using the pull-up resistor setting register (rdr0). the setting does not apply for ports set as outputs (d07 to d00 = 1: invalid at the output setting). ad00 to ad07 in external bus mode, the pins function as the lower data i/o or lower address outputs (ad00 to ad07). 91 to 98 93 to 100 p10 to p17 e (stbc) general-purpose i/o ports pull-up resistors can be set (rd17 to rd10 = 1) using the pull-up resistor setting register (rdr1). the setting does not apply for ports set as outputs (d17 to d10 = 1: invalid at the output setting). ad08 to ad15 in 16-bit external bus mode, the pins function as the upper data i/o or middle address outputs (ad08 to ad15). 99, 100, 1 to 6 1, 2, 3 to 8 p20, p21, p22 to p27 i (stbc) general-purpose i/o ports in external bus mode, pins for which the corresponding bit in the hacr register is 0 function as the p20 to p27 pins. a16, a17, a18 to a23 in external bus mode, pins for which the corresponding bit in the hacr register is 1 function as the upper address output pins (a16 to a23). 79p30 i (stbc) general-purpose i/o port functions as the ale pin in external bus mode. ale functions as the address latch enable signal. 810p31 i (stbc) general-purpose i/o port functions as the rd pin in external bus mode. rd functions as the read strobe output (rd ). 10 12 p32 i (stbc) general-purpose i/o port functions as the wrl pin in external bus mode if the wre bit in the ecsr register is 1. wrl functions as the lower data write strobe output (wrl ).
7 mb90650a series (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 11 13 p33 i (stbc) general-purpose i/o port functions as the wrh pin in 16-bit external bus mode if the wre bit in the ecsr register is 1. wrh functions as the upper data write strobe output (wrh ). 12 14 p34 i (stbc) general-purpose i/o port functions as the hrq pin in external bus mode if the hde bit in the ecsr register is 1. hrq functions as the hold request input pin (hrq). 13 15 p35 i (stbc) general-purpose i/o port functions as the hak pin in external bus mode if the hde bit in the ecsr register is 1. hak functions as the hold acknowledge output (hak ) pin. 14 16 p36 i (stbc) general-purpose i/o port functions as the rdy pin in external bus mode if the rye bit in the ecsr register is 1. rdy functions as the external ready input (rdy) pin. 15 17 p37 i (stbc) general-purpose i/o port functions as the clk pin in external bus mode if the cke bit in the ecsr register is 1. clk functions as the machine cycle clock output (clk) pin. 16 18 p40 h (stbc) general-purpose i/o port when uart0 is operating, the data at the pin is used as the serial input (sin0). can be set as an open-drain output port (od40 = 1) by the open-drain control register (odr4). the setting does not apply for ports set as inputs (d40 = 0: invalid at the input setting). sin0 functions as the uart0 serial input (sin0). 17 19 p41 g (stbc) general-purpose i/o port functions as the sot0 pin if the soe bit in the umc register is 1. can be set as an open-drain output port (od41 = 1) by the open-drain control register (odr4). the setting does not apply for ports set as inputs (d41 = 0: invalid at the input setting). sot0 functions as the uart0 serial data output pin (sot0).
8 mb90650a series (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 18 20 p42 h (stbc) general-purpose i/o port when uart0 is operating in external shift clock mode, the data at the pin is used as the clock input (sck0). also, functions as the sck0 pin if the soe bit in the umc register is 1. can be set as an open-drain output port (od42 = 1) by the open-drain control register (odr4). the setting does not apply for ports set as inputs (d42 = 0: invalid at the input setting). sck0 functions as the uart0 serial clock i/o pin (sck0). 19 21 p43 h (stbc) general-purpose i/o port when i/o extended serial is operating, the data at the pin is used as the serial input (sin1). can be set as an open-drain output port (od43 = 1) by the open-drain control register (odr4). the setting does not apply for ports set as inputs (d43 = 0: invalid at the input setting). sin1 functions as the serial input for i/o extended serial data. 20 22 p44 g (stbc) general-purpose i/o port functions as the sot1 pin if the soe bit in the umc register is 1. can be set as an open-drain output port (od44 = 1) by the open-drain control register (odr4). the setting does not apply for ports set as inputs (d44 = 0: invalid at the input setting). sot1 functions as the output pin (sot1) for i/o extended serial data. 22 24 p45 h (stbc) general-purpose i/o port when i/o extended serial is operating in external shift clock mode, the data at the pin is used as the clock input (sck1). also, functions as the sck1 pin if the soe bit in the umc register is 1. can be set as an open-drain output port (od45 = 1) by the open-drain control register (odr4). the setting does not apply for ports set as inputs (d45 = 0: invalid at the input setting). sck1 functions as the i/o extended serial clock i/o pin (sck1). 23 25 p46 g (stbc) general-purpose i/o port can be set as an open-drain output port (od46 = 1) by the open-drain control register (odr4). the setting does not apply for ports set as inputs (d46 = 0: invalid at the input setting). adtg functions as the external trigger input pin for the a/d converter. 24 26 p47 k (nmos/h) (stbc) open-drain type general-purpose i/o port
9 mb90650a series (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 36 to 39, 41 to 44 38 to 41, 43 to 46 p50 to p53, p54 to p57 l (stbc) general-purpose i/o ports an0 to an3, an4 to an7 the pins are used as analog inputs (an0 to an7) when the a/d converter is operating. 57 59 p60 f (stbc) general-purpose i/o port a pull-up resistor can be set (rd60 = 1) using the pull-up resistor setting register (rdr6). the setting does not apply for ports set as outputs (d60 = 1: invalid at the output setting). sin2 functions as a data input pin (sin2) for i/o extended serial. 58 60 p61 e (stbc) general-purpose i/o port function as the sot2 pin if the soe bit in the umc register is 1. a pull-up resistor can be set (rd61 = 1) using the pull-up resistor setting register (rdr6). the setting does not apply for ports set as outputs (d61 = 1: invalid at the output setting). sot2 functions as an output pin (sot2) for i/o extended serial data. 59 61 p62 f (stbc) general-purpose i/o port when i/o extended serial is operating in external shift clock mode, the data at the pin is used as the clock input (sck2). also, functions as the sck2 pin if the soe bit in the umc register is 1. a pull-up resistor can be set (rd62 = 1) using the pull-up resistor setting register (rdr6). the setting does not apply for ports set as outputs (d62 = 1: invalid at the output setting). sck2 functions as the i/o extended serial clock i/o pin (sck2). 60 62 p63 e (stbc) general-purpose i/o port a pull-up resistor can be set (rd63 = 1) using the pull-up resistor setting register (rdr6). the setting does not apply for ports set as outputs (d63 = 1: invalid at the output setting). ppg00 functions as the ppg00 output when ppg output is enabled. 61 63 p64 e (stbc) general-purpose i/o port a pull-up resistor can be set (rd64 = 1) using the pull-up resistor setting register (rdr6). the setting does not apply for ports set as outputs (d64 = 1: invalid at the output setting). ppg01 functions as the ppg01 output when ppg output is enabled.
10 mb90650a series (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 62 64 p65 e (stbc) general-purpose i/o port a pull-up resistor can be set (rd65 = 1) using the pull-up resistor setting register (rdr6). the setting does not apply for ports set as outputs (d65 = 1: invalid at the output setting). ckot functions as the ckot output when ckot is operating. 63 65 p66 e (stbc) general-purpose i/o port a pull-up resistor can be set (rd66 = 1) using the pull-up resistor setting register (rdr6). the setting does not apply for ports set as outputs (d66 = 1: invalid at the output setting). ppg10 functions as the ppg10 output when ppg output is enabled. 64 66 p67 e (stbc) general-purpose i/o port a pull-up resistor can be set (rd67 = 1) using the pull-up resistor setting register (rdr6). the setting does not apply for ports set as outputs (d67 = 1: invalid at the output setting). ppg11 functions as the ppg11 output when ppg output is enabled. 25 27 p70 k (nmos/h) (stbc) open-drain type i/o port sda i 2 c interface data i/o pin this function is valid when i 2 c interface operations are enabled. set port output to hi-z (pdr = 1) during i 2 c interface operations. 26 28 p71 k (nmos/h) (stbc) open-drain type i/o port scl i 2 c interface clock i/o pin this function is valid when i 2 c interface operations are enabled. set port output to hi-z (pdr = 1) during i 2 c interface operations. 27 29 p72 k (stbc) open-drain type i/o port 30 32 p73 m (stbc) open-drain type i/o port functions as a d/a output pin when dae0 = 1 in the d/a control register (dacr). da00 functions as d/a output 0 when the d/a converter is operating. 31 33 p74 m (stbc) general-purpose i/o port functions as a d/a output pin when dae1 = 1 in the d/a control register (dacr). da01 functions as d/a output 1 when the d/a converter is operating. 45 47 p80 j general-purpose i/o port irq0 functions as external interrupt request i/o 0.
11 mb90650a series (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 46 48 p81 j general-purpose i/o port irq1 functions as external interrupt request i/o 1. 51 53 p82 j general-purpose i/o port irq2 functions as external interrupt request i/o 2. 52 54 p83 j general-purpose i/o port irq3 functions as external interrupt request i/o 3. 53 55 p84 j general-purpose i/o port irq4 functions as external interrupt request i/o 4. 54 56 p85 j general-purpose i/o port irq5 functions as external interrupt request i/o 5. 55 57 p86 i (stbc) general-purpose i/o port this applies in all cases. out3 event output for channel 3 of the output compare 65 67 p90 j general-purpose i/o port ain0 input to channel 0 of the 8/16-bit up/down counter/timer irq6 functions as an interrupt request input. 66 68 p91 j (stbc) general-purpose i/o port bin0 input to channel 0 of the 8/16-bit up/down counter/timer 67 69 p92 j (stbc) general-purpose i/o port zin0 input to channel 0 of the 8/16-bit up/down counter/timer 68 70 p93 j general-purpose i/o port ain1 input to channel 1 of the 8/16-bit up/down counter/timer irq7 functions as an interrupt request input. 69 71 p94 j (stbc) general-purpose i/o port bin1 input to channel 1 of the 8/16-bit up/down counter/timer 70 72 p95 j (stbc) general-purpose i/o port zin1 input to channel 1 of the 8/16-bit up/down counter/timer 71 73 p96 j (stbc) general-purpose i/o port in0 trigger input for channel 0 of the input capture 72 74 p97 j (stbc) general-purpose i/o port in1 trigger input for channel 1 of the input capture 73 75 pa0 i (stbc) general-purpose i/o port out0 event output for channel 0 of the output compare
12 mb90650a series (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 note: stbc = incorporates standby control nmos = n-ch open-drain output pin no. pin name circuit type function lqfp* 1 qfp* 2 74 76 pa1 i (stbc) general-purpose i/o port out1 event output for channel 1 of the output compare 76 78 pa2 i (stbc) general-purpose i/o port out2 event output for channel 2 of the output compare 82 84 v cc 1 power supply (3.0 v) input pin 21 23 v cc 2 power supply (3.0 v/5.0 v) input pin 9, 40, 79 11, 42, 81 v ss power supply (0.0 v) input pin 32 34 av cc a/d converter power supply pin 33 35 avrh a/d converter external reference power supply pin 34 36 avrl a/d converter external reference power supply pin 35 37 av ss a/d converter power supply pin 28 30 dvrh d/a converter external reference power supply pin 29 31 dv ss d/a converter power supply pin 56 58 dtmf n dtmf output pin
13 mb90650a series n i/o circuit type (continued) type circuit remarks a ? oscillation feedback resistance : approx. 1 m w b ? oscillation feedback resistance : approx. 10 m w c ? hysteresis input with pull-up resistance approx. 50 k w d ? hysteresis input port e ? incorporates pull-up resistor control (for input) ? cmos level i/o resistance approx. 50 k w f ? incorporates pull-up resistor control (for input) ? cmos level output ? hysteresis input resistance approx. 50 k w x1 x0 standby control signal x1a x0a standby control signal hysteresis input r r hysteresis input r ctl cmos r ctl hysteresis input r
14 mb90650a series (continued) type circuit remarks g ? cmos level i/o ? incorporates open-drain control h ? cmos level output ? hysteresis input ? incorporates open-drain control i ? cmos level i/o j ? cmos level output ? hysteresis input k ? hysteresis input ? n-ch open-drain output l ? cmos level i/o ? analog input open-drain control signal cmos r hysteresis input open-drain control signal r cmos r hysteresis input r hysteresis input digital output r cmos r analog input
15 mb90650a series (continued) type circuit remarks m ? cmos level i/o ? analog output ? shared with d/a outputs n ? dtmf analog output cmos d/a output r r r r
16 mb90650a series n handling devices 1. preventing latch-up latch-up occurs in a cmos ic if a voltage greater than v cc or less than v ss is applied to an input or output pin or if the voltage applied between v cc and v ss exceeds the rating. if latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. therefore, ensure that maximum ratings are not exceeded in circuit operation. for the same reason, also ensure that the analog supply voltage does not exceed the digital supply voltage. 2. treatment of unused pins leaving unused input pins unconnected can cause misoperation. always pull-up or pull-down unused pins. 3. external reset input to reliably reset the controller by inputting an l level to the rst pin, ensure that the l level is applied for at least five machine cycles. take particular note when using an external clock input. 4. v cc and v ss pins ensure that all v cc pins are at the same voltage. the same applies for the v ss pins. 5. precautions when using an external clock drive the x0 pin only when using an external clock. 6. a/d converter power supply and the turn-on sequence for analog inputs always turn off the a/d converter power supply (av cc , avrh, avrl) and analog inputs (an0 to an7) before turning off the digital power supply (v cc ). when turning the power on or off, ensure that avrh does not exceed av cc . also, when using the analog input pins as input ports, ensure that the input voltage does not exceed av cc . 7. turn-on sequence for d/a converter power supply always turn on the d/a converter power supply (dvr), after turning off the digital power supply (v cc ). and in the turning off the power supply sequence always turn off the digital power supply (v cc ) after turning off the d/a converter power supply (dvr). x0 x1 mb90650a series ? using an external clock
17 mb90650a series 8. initializing in this device there are some kinds of inner resisters which are initializid only by power on reset. it is possible to initialize these resisters by turning on the power supply again. 9. power supply pins when there are several v cc and v ss pins, those pins that should have the same electric potential are connected within the device when the device is designed in order to prevent misoperation, such as latchup. however, all of those pins must be connected to the power supply and ground externally in order to reduce unnecessary emissions, prevent misoperation of strobe signals due to an increase in the ground level, and to observe the total output current standards. in addition, give a due consideration to the connection in that current supply be connected to v cc and v ss with the lowest possible impedance. finally, it is recommended to connect a capacitor of about 0.1 m f between v cc and v ss near this device as a bypass capacitor. 10.crystal oscillation circuit noise in the vicinity of the x0 and x1 pins will cause this device to operate incorrectly. design the printed circuit board so that the bypass capacitor connecting x0, x1 and the crystal oscillator (or ceramic oscillator) to ground is located as close to the device as possible, and that the wiring does not closs the other wirings. in addition, because printed circuit board artwork in which the area around the x0 and x1 pins is surrounded by ground provides stable operation, such an arrangement is strongly recommended. 11. about 2 power supplies the mb90650a series usually uses the 3-v power supply as the main power source. with vcc1 = 3 v and vcc2 = 5 v, however, it can interface with p20 to p27, p30 to p37, p40 to p47, and p70 to p72 for the 5-v power supply separately from the 3-v power supply. note, however, that the analog power supplies such as a/d and d/a can be used only as 3-v power supplies.
18 mb90650a series n programming for mb90p653a in eprom mode, the mb90p653a functions equivalent to the mbm27c1000/1000a. this allows the eprom to be programmed with a general-purpose eprom programmer by using the dedicated socket adapter (do not use the electronic signature mode). 1. program mode when shipped from fujitsu, and after each erasure, all bits (128 k 8 bits) in the mb90p653a are in the 1 state. data is written to the rom by selectively programming 0 into the desired bit locations. bits cannot be set to 1 electrically. 2. programming procedure (1) set the eprom programmer to mbm27c1000/1000a. (2) load program data into the eprom programmer at 00000 h to 1ffff h . note that rom addresses fe0000 h to ffffff h in the operation mode in the mb90p653a series assign to 00000 h to 1ffff h in the eprom mode (on the eprom programmer). the 00 bank prom mirror is 48 kbytes. (this is a mirror for ff4000 h to ffffff h .) (3) mount the mb90p653a on the adapter socket, then fit the adapter socket onto the eprom programmer. when mounting the device and the adapter socket, pay attention to their mounting orientations. (4) start programming the program data to the device. (5) if programming has not successfully resulted, connect a capacitor of approx. 0.1 m f between v cc and gnd, between v pp and gnd. note: the mask rom products (MB90653A, mb90652a) does not support eprom mode. data cannot, therefore, be read by the eprom programmer. prom ffffff h 010000 h 004000 h 000000 h 1ffff h 00000 h fe0000 h normal operating mode eprom mode prom prom mirror
19 mb90650a series 3. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel: (81)-3-3986-0403 fax: (81)-3-5396-9106 4. recommended screening conditions high temperature aging is recommended as the pre-assembly screening procedure. 5. programming yeild mb90p653a cannot be write tested for all bits due to their nature. therefore the write yield cannot always be guaranteed to be 100%. part no. mb90652apfv MB90653Apfv mb90p653apfv mb90652apf MB90653Apf mb90p653apf package lqfp-100 qfp-100 compatible socket adapter sun hayato co., ltd. rom-100sqf-32dp-16l rom-100qf-32dp-16l program, verify aging +150 c, 48 hrs. data verification assembly
20 mb90650a series 6. eprom mode pin assignments ? mbm27c1000/1000a compatible pins ? non-mbm27c1000/1000a compatible pins power supply, gnd connection pins mbm27c1000/1000a mb90p653a mbm27c1000/1000a mb90p653a pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v pp md2 32 v cc v cc 2oe p32 31 pgm p33 3a15 p17 30n.c. 4 a12 p14 29 a14 p16 5 a07 p27 28 a13 p15 6 a06 p26 27 a08 p10 7 a05 p25 26 a09 p11 8 a04 p24 25 a11 p13 9 a03 p23 24 a16 p30 10 a02 p22 23 a10 p12 11 a01 p21 22 ce p31 12 a00 p20 21 d07 p07 13 d00 p00 20 d06 p06 14 d01 p01 19 d05 p05 15 d02 p02 18 d04 p04 16 gnd v ss 17 d03 p03 pin no. pin name treatment see pin assign- ment md0 md1 x0 x0a connect a pull-up resistor of 4.7 k w . x1 to x1a open av cc avrh p37 p40 to p47 p50 to p57 p60 to p67 p70 to p74 p80 to p86 p90 to p97 pa 0 t o pa 2 n.c. test connect a pull-up resistor of about 1 m w to each pin. classification pin no. pin name power supply see pin assignment hst v cc dvrh gnd see pin assignment p34 p35 p36 rst avrl av ss dv ss v v see pin assignment see pin assignment
21 mb90650a series n block diagram clock control circuit ram interrupt controller 8/16-bit up/down counter/timer 8 bits 2 channels (16 bits 1 channel) 8 8 8 8 8 8 8 57 p00 to p07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p74 p80 to p86 i/o ports cpu f 2 mc-16l family core rom prescaler 16-bit i/o timers in0, in1 out1 to out3 dtp/external interrupt 8 p90 to p97 2 6 irq0 to irq5 irq6, irq7 3 pa0 to pa2 5 x0, x1 rst x0a, x1a ckot (output switching) 1 channel uart sin0 sot0 sck0 sin1, sin2 sot1, sot2 sck1, sck2 a/d converter (10 bits) av cc avrh, avrl av ss adtg an0 to an7 communications prescaler d/a converter (8 bits) 16-bit input capture 2 channels 16-bit output compare 4 channels 16-bit free-run timer 1 channel ain0, ain1 bin0, bin1 zin0, zin1 2 2 2 2 2 8 da00, da01 dvrh dv ss p00 to p07 (8 pins) : incorporates a pull-up resistor setting register (for input) p10 to p17 (8 pins) : incorporates a pull-up resistor setting register (for input) p60 to p67 (8 pins) : incorporates a pull-up resistor setting register (for input) p40 to p46 (7 pins) : incorporates an open-drain setting register p47, p70 to p72 (4 pins) : open-drain ppg00, ppg01 ppg10, ppg11 8/16-bit ppg internal data bus 4 2 2 i 2 c interface scl sda 2 2 2 2 i/o extended serial interface 2 channels test, ad00 to ad15, a16 to a23, ale, rd, wrl, wrh, hrq, hak, rdy, clk, n.c., md0 to md2, v cc , v ss other pins dtmf dtmf
22 mb90650a series n memory map ? mb90652, mb90653, mb90p653 notes: while the rom data image of bank ff can be seen in the upper portion of bank 00, this is done only to permit effective use of the c compilers small model. because the lower 16 bits are the same, it is possible to reference tables in rom without declaring the far specification in the pointer. for example, to access to 00c000 h is to access to the rom content of ffc000 h in practice. because the rom area of ff bank exceeds 48 kbytes, all the area can be seen in bank 00. so, the image for ff4000 h to ffffff h can be seen in bank 00, while fe0000 h to ff3fff h can only be seen in bank ff and fe. rom area ffffff h address #1 fe0000 h 010000 h address #2 004000 h 002000 h address #3 000100 h 0000c0 h 000000 h single chip mode internal rom/external bus mode external rom/external bus mode rom area rom area (ff bank image) rom area (ff bank image) ram registers ram registers ram registers peripherals peripherals peripherals : internal access memory : external access memory : no access * : address #1, #2, and #3 are different owing to their devices respectively. type address #1 address #2 mb90652 mb90653 mb90p653 ff0000 h fe0000 h fe0000 h 004000 h 004000 h 004000 h 000cff h 0014ff h 0014ff h address #3 * * *
23 mb90650a series ? mb90654a, mb90f654a notes: while the rom data image of bank ff can be seen in the upper portion of bank 00, this is done only to permit effective use of the c compilers small model. because the lower 16 bits are the same, it is possible to reference tables in rom without declaring the far specification in the pointer. for example, to access to 00c000 h is to access to the rom content of ffc000 h in practice. because the rom area of ff bank exceeds 48 kbytes, all the area can be seen in bank 00. so, the image for ff4000 h to ffffff h can be seen in bank 00, while fe0000 h to ff3fff h can only be seen in bank ff and fe. ffffff h 010000 h 002100 h 000100 h 0000c0 h 000000 h ram ram ram registers registers registers peripherals peripherals peripherals rom area (ff bank image) rom area (ff bank image) rom area mb90654a* mb90f654a* fc0000 h fc0000 h 004000 h 004000 h 0020ff h 0020ff h : internal access memory : external access memory : no access type address #1 address #2 address #3 * : in the mb90654a and mb90f654a, ram area 2000h is 2100h.
24 mb90650a series n f 2 mc-16l cpu programming model maximum 32 banks r7 r6 r5 r4 r3 r2 r1 r0 rw3 rw2 rw1 rw0 16 bits 000180 h + rp 10 h ? rw7 rw6 rw5 rw4 rl3 rl2 rl1 rl0 ilm rp istnzvc ccr ah al dpr pcb dtb usb ssb adb 8 bits 16 bits 32 bits accumulator usp ssp ps pc user stack pointer system stack pointer processor status program counter user stack upper register system stack upper register user stack lower register system stack lower register direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register uspcu sspcu uspcl sspcl dedicated registers general-purpose registers processor status (ps)
25 mb90650a series n i/o map (continued) address register register name read/ write resource name initial value 00 h port 0 data register pdr0 r/w port 0 xxxxxxxx b 01 h port 1 data register pdr1 r/w port 1 xxxxxxxx b 02 h port 2 data register pdr2 r/w port 2 xxxxxxxx b 03 h port 3 data register pdr3 r/w port 3 xxxxxxxx b 04 h port 4 data register pdr4 r/w port 4 1xxxxxxx b 05 h port 5 data register pdr5 r/w port 5 xxxxxxxx b 06 h port 6 data register pdr6 r/w port 6 xxxxxxxx b 07 h port 7 data register pdr7 r/w port 7 CCCxx111 b 08 h port 8 data register pdr8 r/w port 8 Cxxxxxxx b 09 h port 9 data register pdr9 r/w port 9 xxxxxxxx b 0a h port a data register pdra r/w port a CCCCCxxx b 0b h to 0f h (reserved area) 10 h port 0 direction register ddr0 r/w port 0 0 00 0 00 00 b 11 h port 1 direction register ddr1 r/w port 1 0 00 0 00 00 b 12 h port 2 direction register ddr2 r/w port 2 0 00 0 00 00 b 13 h port 3 direction register ddr3 r/w port 3 0 00 0 00 00 b 14 h port 4 direction register ddr4 r/w port 4 C 00 0 00 00 b 15 h port 5 direction register ddr5 r/w port 5 0 00 0 00 00 b 16 h port 6 direction register ddr6 r/w port 6 0 00 0 00 00 b 17 h port 7 direction register ddr7 r/w port 7 C CC 0 0C CC b 18 h port 8 direction register ddr8 r/w port 8 C 00 0 00 00 b 19 h port 9 direction register ddr9 r/w port 9 0 00 0 00 00 b 1a h port a direction register ddra r/w port a C CC C C0 00 b 1b h port 4 pin register odr4 r/w port 4 C 00 0 00 00 b 1c h port 0 resistance register rdr0 r/w port 0 0 00 0 00 00 b 1d h port 1 resistance register rdr1 r/w port 1 0 00 0 00 00 b 1e h port 6 resistance register rdr6 r/w port 6 0 00 0 00 00 b 1f h analog input enable register ader r/w port 5, a/d 1 11 1 11 11 b 20 h serial mode register 0 smr0 r/w uart0 00000000 b 21 h serial control register 0 scr0 r/w 00000100 b 22 h serial input register/ serial output register 0 sidr/ sodr0 r/w xxxxxxxx b
26 mb90650a series (continued) address register register name read/ write resource name initial value 23 h serial status register 0 ssr0 r/w uart0 0 00 0 1C 00 b 24 h serial mode control status register 0 smcs0 r/w i/o extended serial interface 0 CCCC0000 b 25 h serial mode control status register 0 smcs0 r/w 0 0 0 0 0 0 1 0 b 26 h serial data register 0 sdr0 r/w xxxxxxxx b 27 h clock division control register cdcr r/w communications prescaler 0CCC1111 b 28 h serial mode control status register 1 smcs1 r/w i/o extended serial interface 1 CCCC0000 b 29 h serial mode control status register 1 smcs1 r/w 0 0 0 0 0 0 1 0 b 2a h serial data register 1 sdr1 r/w xxxxxxxx b 2b h to 2f h (reserved area) 30 h interrupt/dtp enable register enir r/w dtp/external interrupts 00000000 b 31 h interrupt/dtp source register eirr r/w 0 00 0 00 00 b 32 h request level setting register elvr r/w 00000000 b 33 h 00000000 b 34 h to 35 h (reserved area) 36 h control status register 1 adcs1 r/w a/d converter 00000000 b 37 h control status register 2 adcs2 0 00 0 00 00 b 38 h data register 1 adcr1 r xxxxxxxx b 39 h data register 2 adcr2 xxxxxxxx b 3a h d/a converter data register 0 dat0 r/w d/a converter xxxxxxxx b 3b h d/a converter data register 1 dat1 r/w xxxxxxxx b 3c h d/a control register channel 0 dacr0 r/w CCCCCCC0 b 3d h d/a control register channel 1 dacr1 r/w CCCCCCC0 b 3e h clock control register clkr r/w clock output control register CCCC0000 b 3f h (reserved area) 40 h reload register lower channel 0 prll0 r/w 8/16-bit ppg xxxxxxxx b 41 h reload register upper channel 0 prlh0 r/w xxxxxxxx b 42 h reload register lower channel 1 prll1 r/w xxxxxxxx b 43 h reload register upper channel 1 prlh1 r/w xxxxxxxx b 44 h ppg0 operation mode control register channel 0 ppgc0 r/w 0x000xx1 b 45 h ppg1 operation mode control register channel 1 ppgc1 r/w 0x000001 b 46 h ppg0, ppg1 output control register channel 0, channel 1 ppgoe r/w 00000000 b 47 h to 4f h (reserved area) 50 h lower compare register channel 0 occp0 r/w 16-bit i/o timer output compare (channel 0 to channel 3) xxxxxxxx b
27 mb90650a series (continued) address register register name read/ write resource name initial value 51 h upper compare register channel 0 occp0 r/w 16-bit i/o timer output compare (channel 0 to channel 3) xxxxxxxx b 52 h lower compare register channel 1 occp1 r/w xxxxxxxx b 53 h upper compare register channel 1 xxxxxxxx b 54 h lower compare register channel 2 occp2 r/w xxxxxxxx b 55 h upper compare register channel 2 xxxxxxxx b 56 h lower compare register channel 3 occp3 r/w xxxxxxxx b 57 h upper compare register channel 3 xxxxxxxx b 58 h compare control status register channel 0 ocs0 r/w 0000CC00 b 59 h compare control status register channel 1 ocs1 r/w CCC00000 b 5a h compare control status register channel 2 ocs2 r/w 0000CC00 b 5b h compare control status register channel 3 ocs3 r/w CCC00000 b 5c h to 5f h (reserved area) 60 h lower input capture register channel 0 ipcp0 r 16-bit i/o timer input capture (channel 0, channel 1) xxxxxxxx b 61 h upper input capture register channel 0 r xxxxxxxx b 62 h lower input capture register channel 1 ipcp1 r xxxxxxxx b 63 h upper input capture register channel 1 r xxxxxxxx b 64 h input capture control status register ics0, 1 r/w 0 00 00 0 00 b 65 h (reserved area) 66 h lower timer data register tcdtl r/w 16-bit i/o timer free-run timer 00000000 b 67 h upper timer data register tcdth r/w 00000000 b 68 h timer control status register tccs r/w 0 00 00 0 00 b 69 h to 6f h (reserved area) 70 h up/down count register channel 0 udcr0 r 8/16-bit up/down counter/timer 00000000 b 71 h up/down count register channel 1 udcr1 0 00 00 0 00 b 72 h reload compare register channel 0 rcr0 w 00000000 b 73 h reload compare register channel 1 rcr1 0 00 00 0 00 b 74 h counter status register channel 0 csr0 r/w 0 00 00 0 00 b 75 h (reserved area) 76 h counter control register channel 0 ccrl0 r/w 8/16-bit up/down counter/timer 00001000 b 77 h ccrh0 0 00 00 0 00 b 78 h counter status register channel 1 csr1 r/w 0 00 00 0 00 b 79 h (reserved area) 7a h counter control register channel 1 ccrl1 r/w 8/16-bit up/down counter/timer 00000000 b
28 mb90650a series (continued) address register register name read/ write resource name initial value 7b h counter control register channel 1 ccrh1 r/w 8/16-bit up/down counter/timer x0001000 b 7c h to 7f h (reserved area) 80 h i 2 c bus status register ibsr r i 2 c interface 00000000 b 81 h i 2 c bus control register ibcr r/w 0 00 00 0 00 b 82 h i 2 c bus clock control register iccr r/w CC 0xxxxx b 83 h i 2 c bus address register iadr r/w C xxxxxxx b 84 h i 2 c bus data register idar r/w xxxxxxxx b 85 h to 87 h (reserved area) 88 h dtmf control register dtmc 00000000 b 89 h dtmf data register dtmd 000x0000 b 8a to 9e h (reserved area) (accessing 90 h to 9e h is prohibited) 9f h delayed interrupt generation/ release register dirr r/w delayed interrupt generation module CCCCCCC0 b a0 h low-power consumption mode control register lpmcr r/w low-power consumption mode 00011000 b a1 h clock selection register ckscr r/w low-power consumption mode 11111100 b a2 h to a4 h (reserved area) a5 h auto-ready function selection register arsr w external bus pin control circuit 0011CC00 b a6 h external address output control register hacr w external bus pin control circuit 00000000 b a7 h bus control signal selection register ecsr w external bus pin control circuit 0000*00C b a8 h watchdog timer control register wdtc r/w watchdog timer xxxxx111 b a9 h timebase timer control register tbtc r/w timebase timer 1C C 00 0 00 b aa h watch timer control register wtc r/w watch timer 1xC00000 b ab h to af h (reserved area)
29 mb90650a series (continued) about programming r/w : readable and writable r : read only w : write only explanation of initial values 0: the initial value of this bit is 0. 1: the initial value of this bit is 1. * : the initial value of this bit is 0 or 1. x: the initial value of this bit is undefined. C: this bit is not used. the initial value is undefined. note: areas below address 0000ff h not listed in the table are reserved areas. these addresses are accessed by internal access. no access signals are output on the external bus. address register register name read/ write resource name initial value b0 h interrupt control register 00 icr00 r/w interrupt controller 00000111 b b1 h interrupt control register 01 icr01 r/w 0 00 00 1 11 b b2 h interrupt control register 02 icr02 r/w 0 00 00 1 11 b b3 h interrupt control register 03 icr03 r/w 0 00 00 1 11 b b4 h interrupt control register 04 icr04 r/w 0 00 00 1 11 b b5 h interrupt control register 05 icr05 r/w 0 00 00 1 11 b b6 h interrupt control register 06 icr06 r/w 0 00 00 1 11 b b7 h interrupt control register 07 icr07 r/w 0 00 00 1 11 b b8 h interrupt control register 08 icr08 r/w 0 00 00 1 11 b b9 h interrupt control register 09 icr09 r/w 0 00 00 1 11 b ba h interrupt control register 10 icr10 r/w 0 00 00 1 11 b bb h interrupt control register 11 icr11 r/w 0 00 00 1 11 b bc h interrupt control register 12 icr12 r/w 0 00 00 1 11 b bd h interrupt control register 13 icr13 r/w 0 00 00 1 11 b be h interrupt control register 14 icr14 r/w 0 00 00 1 11 b bf h interrupt control register 15 icr15 r/w 0 00 00 1 11 b c0 h to ff h (external area)
30 mb90650a series n interrupt vector and interrupt control register assignments to interrupt sources : indicates that the interrupt request flag is cleared by the i 2 os interrupt clear signal. : indicates that the interrupt request flag is cleared by the i 2 os interrupt clear signal (stop request present). : indicates that the interrupt request flag is not cleared by the i 2 os interrupt clear signal. note: for resources in which two interrupt sources share the same interrupt number, the i 2 os interrupt clear signal clears both interrupt request flags. interrupt source i 2 os support interrupt vector interrupt control register number address number address reset #08 ffffdc h int 9 instruction #09 ffffd8 h exception #10 ffffd4 h a/d converter #11 ffffd0 h icr00 0000b0 h timebase timer interval interrupt #12 ffffcc h dtp/external interrupt 0 (external interrupt 0) #13 ffffc8 h icr01 0000b1 h 16-bit free-run timer (i/o timer) overflow #14 ffffc4 h i/o extended serial interface 1 #15 ffffc0 h icr02 0000b2 h dtp/external interrupt 1 (external interrupt 1) #16 ffffbc h i/o extended serial interface 2 #17 ffffb8 h icr03 0000b3 h dtp/external interrupt 2 (external interrupt 2) #18 ffffb4 h dtp/external interrupt 3 (external interrupt 3) #19 ffffb0 h icr04 0000b4 h 8/16-bit ppg 0 counter borrow #20 ffffac h 8/16-bit up/down counter/timer 0 compare #21 ffffa8 h icr05 0000b5 h 8/16-bit up/down counter/timer 0 underflow/overflow, up/down invert #22 ffffa4 h 8/16-bit ppg 1 counter borrow #23 ffffa0 h icr06 0000b6 h dtp/external interrupt 4/5 (external interrupt 4/5) #24 ffff9c h output compare (channel 2) match (i/o timer) #25 ffff98 h icr07 0000b7 h output compare (channel 3) match (i/o timer) #26 ffff94 h watch prescaler #27 ffff90 h icr08 0000b8 h dtp/external interrupt 6 (external interrupt 6) #28 ffff8c h 8/16-bit up/down counter/timer 1 compare #29 ffff88 h icr09 0000b9 h 8/16-bit up/down counter/timer 1 underflow/overflow, up/down invert #30 ffff84 h input capture (channel 0) read (i/o timer) #31 ffff80 h icr10 0000ba h input capture (channel 1) read (i/o timer) #32 ffff7c h output compare (channel 0) match (i/o timer) #33 ffff78 h icr11 0000bb h output compare (channel 1) match (i/o timer) #34 ffff74 h completion of flash memory write/erase #35 ffff70 h icr12 0000bc h dtp/external interrupt 7 (external interrupt 7) #36 ffff6c h uart0 receive complete #37 ffff68 h icr13 0000bd h uart0 transmit complete #39 ffff60 h icr14 0000be h i 2 c interface #41 ffff58 h icr15 0000bf h delayed interrupt generation module #42 ffff54 h
31 mb90650a series n peripheral resources 1. parallel ports (1) i/o ports each port pin can be specified as either an input or output by its corresponding direction register when the pin is not set for use by a peripheral. when a port is set as an input, reading the data register always reads the value corresponding to the pin level. when a port is set as an output, reading the data register reads the data register latch value. the same applies when reading using a read-modify-write instruction. when used as control outputs, reading the data register reads the control output value, irrespective of the direction register value. note that if a read-modify-write instruction (set bit or similar instruction) is used to set output data in the data register before switching a pin from input to output, the instruction reads the input level at the pin and not the data register latch value. data register direction register data register read data register write direction register write direction register read pin - - - - internal data bus ?block diagram
32 mb90650a series (2) port direction registers address : 000000 h p07 p06 p05 p04 p03 p02 p01 p00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value access initial value access initial value access initial value access initial value access initial value access initial value access initial value access initial value access initial value access initial value access xxxxxxxx b r/w* port 0 data register (pdr0) address : 000001 h p17 p16 p15 p14 p13 p12 p11 p10 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 xxxxxxxx b r/w* port 1 data register (pdr1) address : 000002 h p27 p26 p25 p24 p23 p22 p21 p20 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xxxxxxxx b r/w* port 2 data register (pdr2) address : 000003 h p37 p36 p35 p34 p33 p32 p31 p30 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 xxxxxxxx b r/w* port 3 data register (pdr3) address : 000004 h p47 p46 p45 p44 p43 p42 p41 p40 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1xxxxxxx b r/w* port 4 data register (pdr4) address : 000005 h p57 p56 p55 p54 p53 p52 p51 p50 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 xxxxxxxx b r/w* port 5 data register (pdr5) address : 000006 h p67 p66 p65 p64 p63 p62 p61 p60 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xxxxxxxx b r/w* port 6 data register (pdr6) address : 000007 h p74 p73 p72 p71 p70 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 - - - xx111 b r/w* port 7 data register (pdr7) address : 000008 h p86 p85 p84 p83 p82 p81 p80 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - xxxxxxx b r/w* port 8 data register (pdr8) address : 00000a h pa2pa1pa0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - - xxx b r/w* port a data register (pdra) address : 000009 h p97 p96 p95 p94 p93 p92 p91 p90 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 xxxxxxxx b r/w* port 9 data register (pdr9) r/w x : readable and writable : unused : indeterminate * : the operation of reading or writing to i/o ports is slightly different from reading or writing to memory, as follows. ? input mode read: reads the corresponding pin level. write: writes to the output latch. ? output mode read: reads the value of the data register latch. write: the value is output from the corresponding pin.
33 mb90650a series (3) port direction registers d07 d06 d05 d04 d03 d02 d01 d00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value access initial value access initial value access initial value access initial value access initial value access initial value access initial value access initial value access initial value access initial value access 00000000 b r/w* d17 d16 d15 d14 d13 d12 d11 d10 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00000000 b r/w* d27 d26 d25 d24 d23 d22 d21 d20 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00000000 b r/w* d37 d36 d35 d34 d33 d32 d31 d30 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00000000 b r/w* d46 d45 d44 d43 d42 d41 d40 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 -0000000 b r/w* d57 d56 d55 d54 d53 d52 d51 d50 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00000000 b r/w* d67 d66 d65 d64 d63 d62 d61 d60 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00000000 b r/w* d74 d73 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ---00--- b r/w* d86 d85 d84 d83 d82 d81 d80 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 -0000000 b r/w* da2da1da0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 -----000 b r/w* d97 d96 d95 d94 d93 d92 d91 d90 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00000000 b r/w* r/w : readable and writable : unused address : 000010 h address : 000011 h address : 000012 h address : 000013 h address : 000014 h address : 000015 h address : 000016 h address : 000017 h address : 000018 h address : 000019 h address : 00001a h port 0 direction register (ddr0) port 1 direction register (ddr1) port 2 direction register (ddr2) port 3 direction register (ddr3) port 4 direction register (ddr4) port 5 direction register (ddr5) port 6 direction register (ddr6) port 7 direction register (ddr7) port 8 direction register (ddr8) port a direction register (ddra) port 9 direction register (ddr9)
34 mb90650a series (continued) * : the operation of reading or writing to i/o ports is slightly different from reading or writing to memory, as follows. ? input mode read: reads the corresponding pin level. write: writes to the output latch. ? output mode read: reads the value of the data register latch. write: the value is output from the corresponding pin. when pins are used as ports, the register bits control the corresponding pins as follows. 0: input mode 1: output mode bits are set to 0 by a reset. ? p47, p70 to p72 no ddr for this port. data is always available in this port, so when using p70 and p71 as i 2 c pin, set pdr value to 1. (otherwise when using p70 and p71 by themselves, turn off the i 2 c.) as this port is open-drain output style, so when using this port as an input port, in order to turn off the output transister, set the output data resister value to 1 and add the pull up resister to the external pin.
35 mb90650a series (4) port resistance registers ? register configuration ?block diagram rd07 rd06 rd05 rd04 rd03 rd02 rd01 rd00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value access 00000000 b r/w initial value access 00000000 b r/w initial value access 00000000 b r/w rd17 rd16 rd15 rd14 rd13 rd12 rd11 rd10 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 rd67 rd66 rd65 rd64 rd63 rd62 rd61 rd60 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address : 00001c h port 0 resistance register (rdr0) address : 00001d h port 1 resistance register (rdr1) address : 00001e h port 6 resistance register (rdr6) r/w : readable and writable data register direction register port i/o resistance register pull-up resistor (approx. 50 k w ) internal data bus notes: input resistance register r/w controls the pull-up resistor in input mode. 0: pull-up resistor disconnected in input mode. 1: pull-up resistor connected in input mode. the setting has no meaning in output mode (pull-up resistor disconnected). the direction register (ddr) sets input or output mode. the pull-up resistor is disconnected in hardware standby or stop mode (spl = 1) (high impedance). this function is disabled when using an external bus mode. in this case, do not write to this register.
36 mb90650a series (5) port pin register ? register configuration ?block diagram (6) analog input enable register ? register configuration controls each port 5 pin as follows. 0: port input mode 1: analog input mode set to 1 by a reset. : readable and writable od46 od45 od44 od43 od42 od41 od40 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 : unused address : 00001b h port 4 pin register (odr4) initial value access -0000000 b r/w r/w data register direction register port i/o pin register internal data bus notes: pin register r/w performs open-drain control in output mode. 0: operate as a standard output port in output mode. 1: operate as an open-drain output port in output mode. the setting has no meaning in input mode (output hi-z). the direction register (ddr) sets input or output mode. this function is disabled when using an external bus mode. in this case, do not write to this register. ade7 ade6 ade5 ade4 ade3 ade2 ade1 ade0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w : readable and writable address : 00001f h analog input enable register (ader) initial value 11111111 b access r/w r/w r/w r/w r/w r/w r/w r/w r/w
37 mb90650a series 2. uart the uart is a serial i/o port that can be used for clk asynchronous (start-stop synchronization) or clk synchronous communications. the uart has the following features. ? full duplex, double buffered ? supports asynchronous (start-stop synchronization) and clk synchronous data transfer ? supports multi-processor mode ? built-in dedicated baud rate generator ? supports flexible baud rate setting using an external clock ? error detect function (parity, framing, and overrun) ? nrz type transmission signal ? intelligent i/o service support (1) register configuration asynchronous : 9615 bps, 31250 bps, 4808 bps, 2404 bps and 1202 bps clk synchronous : 1 mbps, 500 kbps, 250 kbps, 125 kbps, 115.2 kbps and 62.5 kbps for a 6, 8, 10, 12, or 16 mhz clock. md1 md0 cs2 cs1 cs0 reserved scke soe bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value initial value initial value initial value initial value 00000000 b pen p sbl cl a/d rec rxe txe bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00000100 b d7 d6 d5 d4 d3 d2 d1 d0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xxxxxxxx b pe ore fre rdrf tdre rie tie bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00001-00 b serial status register 0 (ssr0) md div3 div2 div1 div0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0---1111 b clock division control register (cdcr) cdcr scr ssr sidr (r) /sodr (w) smr 8 bits bit 15 bit 8 bit 7 bit 0 8 bits r/w r w x : readable and writable : read only : write only : unused : indeterminate address : 000020 h serial mode register 0 (smr0) address : 000021 h serial control register 0 (scr0) address : 000022 h address : 000023 h address : 000027 h serial input register/serial output register 0 (sidr/sodr0) r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w w r/w r/w r/w r/w r/w r/w r/w r/w r rrrrr r/w
38 mb90650a series (2) block diagram smr register scr register control signals dedicated baud rate generator 16-bit timer 0 (connected internally) external clock sin0 clock select circuit reception interrupt (to cpu) transmission interrupt (to cpu) reception control circuit start bit detection circuit reception bit counter reception parity counter transmission control circuit transmission start circuit transmission bit counter transmission parity counter reception status determination circuit reception shifter end of reception transmission shifter start of transmission reception error occurrence signal for i 2 os (to cpu) sidr sodr internal data bus md1 md0 cs2 cs1 cs0 scke soe ssr register control signals transmission clock pulses reception clock pulses sot0, sot1 pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre rie tie sck0, sck1
39 mb90650a series 3. i/o extended serial interface i/o extended serial interface consists of an 8-bit serial i/o interface that can perform clock synchronous data transfer. either lsb-first or msb-first data transfer can be selected. the following two serial i/o operation modes are available. ? internal shift clock mode: data transfer is synchronized with the internal clock. ? external shift clock mode: data transfer is synchronized with the clock input from the external pin (sck). by manipulating the general-purpose port that shares the external pin (sck), this mode also enables the data transfer operation to be driven by cpu instructions. (1) register details smd2 smd1 smd0 sie sir busy stop strt bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w *1 r r/w r/w *2 initial value initial value initial value 00000010 b mode bds soe scoe ----0000 b bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r x : readable and writable : read only : unused : indeterminate d7 d6 d5 d4 d3 d2 d1 d0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xxxxxxxx b serial data register 0, 1 (sdr0, sdr1) address : 000025 h 000029 h address : 000024 h 000028 h address : 000026 h 00002a h serial mode control status register 0, 1 (smcs0, smcs1) *1: only 0 can be written. *2: only 1 can be written. reading always returns 0. this register controls the transfer operation mode of the serial i/o. the following describes the function of each bit. bit 3: serial mode selection bit (mode) this bit selects the conditions for starting operation from the halted state. changing the mode during operation is prohibited the bit is initialized to 0 by a reset. the bit is readable and writable. set to 1 when using the intelligent i/o service. mode operation 0 start when strt is set to 1. [initial value] 1 start on reading from or writing to the serial data register. bit 2: transfer direction selection bit (bds: bit direction select) selects as follows at the time of serial data input and output whether the data are to be transferred in the order from lsb to msb or vice versa. mode operation 0 lsb-first [initial value] 1 msb-first
40 mb90650a series (2) block diagram internal data bus internal data bus (msb-first) d0 to d7 transfer direction selection read write sdr (serial data register) internal clock control circuit shift clock counter interrupt request sin1, sin2 sot1, sot2 sck1, sck2 smd2 smd1 smd0 sie sir busy stop strt mode bds d7 to d0 (lsb-first) 21 0 soe scoe
41 mb90650a series 4. a/d converter the a/d converter converts analog input voltages to digital values. the a/d converter has the following features. ? conversion time: minimum of 5.2 m s per channel (for a 16 mhz machine clock) ? uses rc-type successive approximation conversion with a sample and hold circuit. ? 10-bit resolution ? eight program-selectable analog input channels single conversion mode: selectively convert a one channel. scan conversion mode: continuously convert multiple channels. maximum of 8 program- selectable channels. continuous conversion mode : repeatedly convert specified channels. stop conversion mode: convert one channel then halt until the next activation. (enables synchronization of the conversion start timing.) ? an a/d conversion completion interrupt request to the cpu can be generated on the completion of a/d conversion. this interrupt can activate i 2 os to transfer the result of a/d conversion to memory and is suitable for continuous operation. ? activation by software, external trigger (falling edge), or timer (rising edge) can be selected. (1) register configuration md1 md0 ans2 ans1 ans0 ane2 ane1 ane0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value initial value initial value initial value 00000000 b control status register 1 (adcs1) busy int inte paus sts1 sts0 strt da bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00000000 b control status register 2 (adcs2) 76543210 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xxxxxxxx b data register 1 (adcr1) 9 8 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 xxxxxxxx b data register 2 (adcr2) : readable and writable : read only : indeterminate adcs2 adcr2 adcr1 adcs1 8 bits bit 15 bit 8 bit 7 bit 0 8 bits address : 000036 h address : 000037 h address : 000038 h address : 000039 h r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r rrrrrr rr r rrr rr r r/w r x
42 mb90650a series (2) block diagram av cc avrh avrl an0 an1 an2 an3 an4 an5 an6 an7 mpx sample and hold circuit comparator d/a converter successive approximation register data register a/d control register 1 a/d control register 2 adcr1, adcr2 adcs1, adcs2 adtg ppg01 f timer activation trigger activation operating clock prescaler av ss input circuit decoder internal data bus
43 mb90650a series 5. d/a converter d/a converter is an r-2r type d/a converter with 8-bit resolution. the device contains two d/a converters. the d/a control register controls the output of the two d/a converters independently. (1) register configuration address : 00003a h da07 da06 da05 da04 da03 da02 da01 da00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value initial value initial value initial value xxxxxxxx b d/a converter data register 0 (dat0) address : 00003b h da17 da16 da15 da14 da13 da12 da11 da10 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 xxxxxxxx b d/a converter data register 1 (dat1) address : 00003c h dae0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 -------0 b d/a control register channel 0 (dacr0) address : 00003d h dae1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 -------0 b d/a control register channel 1 (dacr1) x : unused : indeterminate r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w : readable and writable
44 mb90650a series (2) block diagram internal data bus da 17 da 16 da 15 da 14 da 13 da 12 da 11 da 10 da 07 da 06 da 05 da 04 da 03 da 02 da 01 da 00 dae1 standby control standby control 2r 2r 2r 2r r r r dvr da17 da16 da15 da11 da10 da output channel 1 dae0 2r 2r 2r 2r r r r dvr da07 da06 da05 da01 da00 da output channel 0 2r 2r
45 mb90650a series 6. 8/16-bit ppg 8/16-bit ppg is an 8-bit reload timer module. the block performs ppg output in which the pulse output is controlled by the operation of the timer. the hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs. the ppg has the following functions. ? 8-bit ppg output in two channels independent operation mode: two independent ppg output channels are available. ? 16-bit ppg output operation mode : one 16-bit ppg output channel is available. ? 8 + 8-bit ppg output operation mode : variable-period 8-bit ppg output operation is available by using the output of channel 0 as the clock input to channel 1. ? ppg output operation : outputs pulse waveforms with variable period and duty ratio. can be used as a d/a converter in conjunction with an external circuit. (1) register configuration address : 000044 h pen0 pe00 pie0 puf0 reserved r/w r/w r/w r/w ? ? initial value 0x000xx1 b ppg0 operation mode control register channel 0 (ppgc0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address : 000045 h pen1 pe10 pie1 puf1 md1 md0 reserved r/w r/w r/w r/w r/w r/w initial value 0x000001 b ppg1 operation mode control register channel 1 (ppgc1) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 : readable and writable : indeterminate address : 000046 h pcs2 pcs1 pcs0 pcm2 pcm1 pcm0 pe11 pe01 r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 b ppg0, ppg1 output control register channel 0, channel 1 (ppgoe) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address : 000041 h 000043 h r/w r/w r/w r/w r/w r/w r/w r/w initial value xxxxxxxx b reload register upper channel 0, channel 1 (prlh0, prlh1) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 address : 000040 h 000042 h r/w r/w r/w r/w r/w r/w r/w r/w initial value xxxxxxxx b reload register lower channel 0, channel 1 (prll0, prll1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w x
46 mb90650a series (2) block diagram ppg0 output latch pcnt (down-counter) s r q ppg00 output enable ppg01 output enable l/h selector prlbh0 ppgc0 peripheral clock divided by 16 peripheral clock divided by 8 peripheral clock divided by 4 peripheral clock divided by 2 peripheral clock prll0 prlh0 l-side data bus h-side data bus ppg00 ppg01 clear invert pen0 reload channel 1-borrow irq count clock selection timebase counter output main clock divided by 512 l/h select pie0 puf0 (operation mode control) a/d converter ? 8/16-bit ppg (channel 0)
47 mb90650a series clear invert ppg1 output latch pcnt (down-counter) s r q ppg10 output enable ppg11 output enable l/h selector prlbh1 ppgc1 prll1 prlh1 l-side data bus h-side data bus ppg10 ppg11 pen1 reload channel 0-borrow irq l/h select pie puf uart peripheral clock divided by 16 peripheral clock divided by 8 peripheral clock divided by 4 peripheral clock divided by 2 peripheral clock count clock selection timebase counter output main clock divided by 512 (operation mode control) ? 8/16-bit ppg (channel 1)
48 mb90650a series 7. 8/16-bit up/down counter/timer 8/16-bit up/down counter/timer is an up/down counter/timer and consists of six event input pins, two 8-bit up/ down counters, two 8-bit reload/compare registers, and their control circuits. (1) main functions ? the 8-bit count register can count in the range 0 to 256 (or 0 to 65535 in 1 16-bit operation mode). ? the count clock selection can select between four different count modes. count modes ? two different internal count clocks are available in timer mode. count clock (at 16 mhz operation) ? in up/down count mode, you can select which edge to detect on the external pin input signal. detected edge ? phase difference count mode is suitable for motor encoder counting. by inputting the a, b, and z phase outputs from the encoder, a high-precision rotational angle, speed, or similar count can be implemented simply. ? two different functions can be selected for the zin pin. zin pin ? compare and reload functions are available and can be used either independently or together. a variable- width up/down count can be performed by activating both functions. compare/reload function ? whether or not to generate an interrupt when a compare, reload (underflow), or overflow occurs can be set independently. ? the previous count direction can be determined from the count direction flag. ? an interrupt can be generated when the count direction changes. timer mode up/down counter mode phase difference count mode ( 2) phase difference count mode ( 8) 125 ns (8 mhz: divide by 2) 0.5 m s (1 mhz: divide by 8) detect falling edges detect rising edges detect both rising and falling edges edge detection disabled counter clear function gate function compare function (output an interrupt when a compare occurs.) compare function (output an interrupt and clear the counter when a compare occurs.) reload function (output an interrupt and reload when an underflow occurs.) compare/reload function (output an interrupt and clear the counter when a compare occurs. output an interrupt and reload when an underflow occurs.) compare/reload disabled
49 mb90650a series (2) register configuration address : 000070 h d07 d06 d05 d04 d03 d02 d01 d00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value initial value initial value initial value initial value initial value initial value initial value 00000000 b up/down count register channel 0 (udcr0) address : 000071 h d17 d16 d15 d14 d13 d12 d11 d10 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00000000 b up/down count register channel 1 (udcr1) address : 000072 h d07 d06 d05 d04 d03 d02 d01 d00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00000000 b reload compare register channel 0 (rcr0) address : 000073 h d17 d16 d15 d14 d13 d12 d11 d10 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00000000 b reload compare register channel 1 (rcr1) address : 000074 h 000078 h cstr cite udie cmpf ovff udff udf1 udf0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 counter status register channel 0, channel 1 (csr0, csr1) ccrh0 (reversed area) ccrh1 ccrl1 csr1 ccrl0 udcr1 rcr1 (reversed area) csr0 rcr0 udcr0 8 bits bit 15 bit 8 bit 7 bit 0 8 bits 00000000 b address : 000076 h 00007a h C C ctut ucre rlde udcc cgsc cge1 cge0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 counter control register channel 0, channel 1 (ccrl0, ccrl1) 00001000 b 00000000 b address : 000077 h m16e cdcf cfie clks cms1 cms0 ces1 ces0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 counter control register channel 0 (ccrh0) 00000000 b address : 00007b h C C cdcf cfie clks cms1 cms0 ces1 ces0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 counter control register channel 1 (ccrh1) x0001000 b rrr r rrrr rrr r rrrr wwwwwwww wwwwwwww r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w rr : readable and writable : read only : write only r/w r w C : unused x : indeterminate
50 mb90650a series (3) block diagram internal data bus cge1 cge0 c/gs carry cms1 cms0 ces1 ces0 cite udie udf1 udf0 cdcf cfie edge or level detection rcr0 (reload/compare register 0) ctut ucre rlde reload control udcc counter clear udcr0 (up/down count register 0) cmpf udff ovff prescaler clks cstr up/down count clock selection count clock interrupt output 8 bits 8 bits ain0 bin0 zin0 ? 8/16-bit up/down counter/timer (channel 0)
51 mb90650a series internal data bus cge1 cge0 c/gs carry cite udie udf1 udf0 cdcf cfie edge or level detection rcr1 (reload/compare register 1) ctut ucre rlde reload control udcc counter clear udcr1 (up/down count register 1) cmpf udff ovff prescaler clks cstr up/down count clock selection count clock interrupt output 8 bits 8 bits ain1 bin1 zin1 cms1 cms0 ces1 ces0 en16 ? 8/16-bit up/down counter/timer (channel 1)
52 mb90650a series 8. clock output control register clock output control register outputs the divided machine clock. (1) register configuration address : 00003e h cken frq2 frq1 frq0 r/w r/w r/w r/w initial value ----0000 b clock control register (clkr) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w : readable and writable : unused bit 3: clock output enable bit (cken) bit 2 to bit 0: clock output frequency select bit (frq2 to frq0) mode operation 0 operate as a standard port. 1 operate as the clock output. frq2 frq1 frq0 output clock f = 16 mhz f = 8 mhz f = 4 mhz 000 f /2 1 125 ns 250 ns 500 ns 001 f /2 2 250 ns 500 ns 1 m s 010 f /2 3 500 ns 1 m s2 m s 011 f /2 4 1 m s2 m s4 m s 100 f /2 5 2 m s4 m s8 m s 101 f /2 6 4 m s8 m s16 m s 110 f /2 7 8 m s16 m s32 m s 111 f /2 8 16 m s32 m s64 m s
53 mb90650a series 9. dtp/external interrupts the dtp (data transfer peripheral) is a peripheral block that interfaces external peripherals to the f 2 mc-16l cpu. the dtp receives dma and interrupt processing requests from external peripherals and passes the requests to the f 2 mc-16l cpu to activate the intelligent i/o service or interrupt processing. two request levels (h and l) are provided for the intelligent i/o service. for external interrupt requests, generation of interrupts on a rising or falling edge as well as on h and l levels can be selected, giving a total of four types. (1) register configuration (2) block diagram address : 000030 h en7 en6 en5 en4 en3 en2 en1 en0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value initial value initial value initial value 00000000 b interrupt/dtp enable register (enir) address : 000031 h er7 er6 er5 er4 er3 er2 er1 er0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00000000 b 00000000 b 00000000 b interrupt/dtp source register (eirr) address : 000032 h lb3 la3 lb2 la2 lb1 la1 lb0 la0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 request level setting register (elvr) address : 000033 h lb7 la7 lb6 la6 lb5 la5 lb4 la4 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w : readable and writable 4 4 4 8 4 interrupt/dtp enable register interrupt/dtp source register request level setting register gate request f/f edge detect circuit request input internal data bus
54 mb90650a series 10. 16-bit i/o timer the 16-bit i/o timer consists of one 16-bit free-run timer, two output compare, and two input capture modules. based on the 16-bit free-run timer, these functions can be used to generate two independent waveform outputs and to measure input pulse widths and external clock periods. ? register configuration ?block diagram tcdtl : 000066 h tcdth : 000067 h bit 15 bit 0 16-bit free-run timer timer data register lower, upper (tcdtl, tcdth) tccs : 000068 h timer control status register (tccs) ipcp0 : 000060 h , 61 h ipcp1 : 000062 h , 63 h bit 15 bit 0 16-bit input capture input capture register channel 0, channel 1 lower, upper (ipcp0, ipcp1) ics0, 1 : 000064 h input capture control status register (ics0, 1) occp0 : 000050 h , 51 h occp1 : 000052 h , 53 h occp2 : 000054 h , 55 h occp3 : 000056 h , 57 h bit 15 bit 0 ocs0 : 000058 h ocs1 : 000059 h ocs2 : 00005a h ocs3 : 00005b h 16-bit output compare compare register channel 0 to channel 3 lower, upper (occp0 to occp3) compare control status register channel 0 to channel 3 (ocs0 to ocs3) tcdt occp ocs ipcp tccs ics 16-bit free-run timer control logic 16-bit timer compare register 0 compare register 1 compare register 2 compare register 3 capture register 0 capture register 1 output compare 0 output compare 1 output compare 2 output compare 3 input capture 0 tq tq tq tq edge selection edge selection interrupt to each block out0 out1 out2 out3 in0 in1 clear internal data bus
55 mb90650a series (1) 16-bit free-run timer the 16-bit free-run timer consists of a 16-bit up-counter, a control register, and a prescaler. the output of the timer/counter is used as the base time for the input capture and output compare. ? the operating clock for the counter can be selected from four different clocks. four internal clocks ( f /4, f /16, f /32, f /64) ? interrupts can be generated when a counter value overflow or compare match with compare register 0 occurs (the appropriate mode must be set for a compare match). ? the counter can be initialized to 0000 h by a reset, software clear, or compare match with compare register 0. ? register details the count value of the 16-bit free-run timer can be read from this register. the count is cleared to 0000 b by a reset. writing to this register sets the timer value. however, only write to the register when the timer is halted (stop = 1). always use word access. the 16-bit free-run timer is initialized by the following. ? reset ? the clear bit (clr) of the control status register ? a match between the timer/counter value and compare register 0 of the output compare (if the appropriate mode is set) ?block diagram address : 000067 h t15 t14 t13 t12 t11 t10 t09 t08 r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 b upper timer data register (tcdth) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w : readable and writable address : 000066 h t07 t06 t05 t04 t03 t02 t01 t00 r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 b lower timer data register (tcdtl) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ivf ivfe stop mode clr clk1 clk0 16-bit up-counter divider comparator 0 clock f count value output t15 to t00 interrupt request internal data bus
56 mb90650a series (2) output compare the output compare consists of two 16-bit compare registers, compare output latches, and control registers. the modules can invert the output level and generate an interrupt when the 16-bit free-run timer value matches the compare register value. ? the four compare registers can be operated independently. each compare register has a corresponding output pin and interrupt flag. ? the four compare registers can be paired to control the output pins. invert the output pins using the four compare registers. ? initial values can be set for the output pins. ? an interrupt can be generated when a compare match occurs. ? register configuration occp0 : 000050 h occp1 : 000052 h occp2 : 000054 h occp3 : 000056 h occp0 : 000051 h occp1 : 000053 h occp2 : 000055 h occp3 : 000057 h upper compare register channel 0 to channel 3 (occp0 to occp3) lower compare register channel 0 to channel 3 (occp0 to occp3) compare control status register channel 0 to channel 3 (ocs0 to ocs3) initial value xxxxxxxx b x : unused : indeterminate c15 c14 c13 c12 c11 c10 c09 c08 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w initial value xxxxxxxx b c07 c06 c05 c04 c03 c02 c01 c00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value ---00000 b cmod ote1 ote0 otdi otd0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w ocs1 : 000059 h ocs3 : 00005b h ocs1 : 000059 h ocs3 : 00005b h initial value 0000--00 b ice0 cst1 cst0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w icp1 icp0 ice1 ocs0 : 000058 h ocs2 : 00005a h : readable and writable r/w
57 mb90650a series ?block diagram icp1 icp0 ice1 ice0 compare control tq control blocks compare 1 interrupt (3) compare register 0 (2) compare control compare register 1 (3) controller 16-bit timer/counter value (t15 to t00) 16-bit timer/counter value (t15 to t00) tq cmod ote1 oteo compare 0 interrupt (2) out0 (out2) out1 (out3) internal data bus
58 mb90650a series (3) input capture the input capture consists of two independent external input pins, their corresponding capture registers, and a control register. the value of the 16-bit free-run timer can be stored in the capture register and an interrupt generated when the specified edge is detected on the signal from the external input pin. ? the edge to detect on the external input signal is selectable. detection of rising edges, falling edges, or either edge can be specified. ? the two input capture channels can operate independently. ? an interrupt can be generated on detection of the specified edge on the external input signal. the input capture interrupt can activate the intelligent i/o service. ? register details the 16-bit free-run timer value is stored in these registers when the specified edge is detected on the input waveform from the corresponding external pin. (always use word access. writing is prohibited.) ?block diagram ipcp0 : 000060 h ipcp1 : 000062 h : read only : indeterminate cp07 cp06 cp05 cp04 cp03 cp02 cp01 cp00 rr r r rr r r r initial value xxxxxxxx b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ipcp0 : 000061 h ipcp1 : 000063 h cp15 cp14 cp13 cp12 cp11 cp10 cp09 cp08 r r r r r r r r initial value xxxxxxxx b x input capture register channel 0, channel 1 (ipcp0, ipcp1) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 000064 h icp1 icp0 ice1 ice0 eg11 eg10 eg01 eg00 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 b input capture control status register (ics0, 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 : readable and writable capture data register 0 edge detection interrupt 16-bit timer/counter value (t15 to t00) interrupt in0 capture data register 1 edge detection eg11 eg10 eg01 eg00 icp1 icp0 ice1 ice0 in1 internal data bus
59 mb90650a series 11. watchdog timer, timebase timer, and watch timer the watchdog timer consists of a 2-bit watchdog counter that uses the carry signal from the 18-bit timebase timer or the 15-bit watch timer as aclock source, a control register, and a watchdog reset controller. the timebase timer consists of an 18-bit timer and a circuit that controls interval interrupts. note that the timebase timer uses the main clock, regardless of the setting of the mcs bit and scs bit in ckscr. the watch timer consists of a 15-bit timer and a circuit that controls interval interrupts. note that the watch timer uses the sub clock, regardless of the setting of the mcs bit scs bit in ckscr. (1) register configuration address : 0000a9 h reserved tbie tbof tbr tbc1 tbc0 ?r/w r/w w r/w r/w initial value 1--00000 b timebase timer control register (tbtc) watch timer control register (wtc) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 address : 0000aa h wdcs sce wtie wtof wtr wtc2 wtc1 wtc0 r/w r r/w r/w r r/w r/w r/w initial value 1x000000 b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 watchdog timer control register (wdtc) address : 0000a8 h ponr wrst erst srst wte wt1 wt0 r r r r w w w initial value xxxxx111 b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r w x : readable and writable : read only : write only : unused : indeterminate
60 mb90650a series (2) block diagram srst erst wrst ponr wdtc from power-on generation rst pin from rst bit in the stbyc register sub clock wtc wdcs sce wtc1 wtc0 wtr wtie wtof and q s r selector q s r and 2 10 wtres 2 10 2 13 2 14 2 15 watch timer clock input scm wdgrst to internal reset generator watchdog reset generator clr 2-bit counter of clr selector wdtc wt1 wt0 wte timebase interrupt tbtc tbc1 tbc0 tbie tbr tbof and q s r selector timebase timer clock input main clock 2 12 2 14 2 16 2 19 tbtres 2 12 2 14 2 16 2 19 internal data bus power-on reset sub clock stops timer interrupt 2 13 2 14 2 15
61 mb90650a series 12. i 2 c interface the i 2 c interface is a serial i/o port that supports the inter-ic bus and operates as a master/slave device on the i 2 c bus. this module has the following features: ? master/slave transmission/reception ? arbitration function ? clock synchronization function ? slave address/general call address detection function ? transfer direction detection function ? start condition repeat generation and detection function ? bus error detection function (1) register configuration address : 000083 h a6a5a4a3a2a1a0 r/w r/w r/w r/w r/w r/w r/w initial value -xxxxxxx b i 2 c bus address register (iadr) i 2 c bus data register (idar) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 address : 000084 h d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w initial value xxxxxxxx b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 i 2 c bus clock control register (iccr) address : 000082 h en cs4 cs3 cs2 cs1 cs0 r/w r/w r/w r/w r/w r/w initial value --0xxxxx b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r x address : 000081 h ber beie scc mss ack gcaa inte int r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 b 00000000 b i 2 c bus control register (ibcr) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 i 2 c bus status register (ibsr) address : 000080 h bb rsc al lrb trx aas gca fbt r r r r r r r r initial value bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 : readable and writable : read only : unused : indeterminate
62 mb90650a series (2) block diagram bb rsc lrb trx fbt al ibsr cs4 cs3 cs2 cs1 cs0 iccr iccr en iadr ber beie inte int ibcr scc mss ack gcaa aas gca ibsr idar interrupt request slave address comparison start/stop condition generation ibcr slave global call start master ack enable gc-ack enable arbitration lost detection clock selection 2 clock divider 2 start/stop condition generation shift clock generation bus busy repeat start last bit first byte error 2 8 16 32 64 128 256 4 clock selection 1 clock divider 1 5678 i 2 c enable peripheral clock irq end scl sda sync shift clock edge change timing transmit/receive internal data bus
63 mb90650a series 13. external bus pin control circuit the external bus pin control circuit controls the external bus pins required to extend the cpus address/data bus outside the device. (1) register configuration (2) block diagram address : 0000a7 h cke rye hde icbs hmbs wre lmbs wwwwwww initial value 0000*00- b bus control signal selection register (ecsr) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 external address output control register (hacr) address : 0000a6 h e23 e22 e21 e20 e19 e18 e17 e16 wwwwwwww initial value 00000000 b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w * address : 0000a5 h icr1 icr0 hmr1 hmr0 lmr1 lmr0 wwww ww initial value 0011--00 b auto-ready function selection register (arsr) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 : write only : unused : ??or ? p3 p2 p1 p0 access control access control p0 address control data control p0 data p0 direction p3 rb
64 mb90650a series 14. low-power consumption mode (cpu intermittent operation function, oscillation stabilization delay time, clock multiplier function) the following are the operating modes: pll clock mode, pll sleep mode, pll watch mode, pseudo-watch mode, main clock mode, main sleep mode, main watch mode, main stop mode, sub clock mode, sub sleep mode, sub watch mode, and sub stop mode. aside from the pll clock mode, all of the other operating modes are low-power consumption modes. in main clock mode and main sleep mode, the main clock (main osc oscillation clock) and the sub clock (sub osc oscillation clock) operate. in these modes, the main clock divided by 2 is used as the operation clock, the sub clock (sub osc oscillation clock) is used as the timer clock, and the pll clock (vco oscillation clock) is stopped. in sub clock mode and sub sleep mode, only the sub clock operates. in these modes, the sub clock is used as the operation clock, and the main clock and pll clock are stopped. in pll sleep mode and main sleep mode, only the cpus operation clock is stopped; all clocks other than the cpu clock operate. in pseudo-watch mode, only the watch timer and timebase timer operate. in pll watch mode, main watch mode, and sub watch mode, only the watch timer operates. in this mode, only the sub clock is used for operation, while the main clock and the pll clock are stopped (the difference between the pll watch mode, the main watch mode and the sub watch mode is that it resumes operation after an interrupt in the pll clock mode, the main clock mode, and the sub clock mode respectively, and there is no reference concerning about clock mode operation). the main stop mode, sub stop mode, and hardware standby mode stop oscillation, making it possible to retain data while consuming the least amount of power. (the difference between the main stop mode and the sub stop mode is that it resumes operation in the main clock mode and the sub clock mode respectively, and there is no reference concerning about stop mode operation). the cpu intermittent operation function intermittently runs the clock supplied to the cpu when accessing registers, on-chip memory, on-chip resources, and the external bus. processing is possible with lower power consumption by reducing the execution speed of the cpu while supplying a high-speed clock and using on-chip resources. the pll clock multiplier can be selected as either 2, 4, 6, or 8 by setting the cs1 and cs0 bits. these clocks are divided by 2 to be used as a machine clock. the ws1 and ws0 bits can be used to set the main clock oscillation stabilization delay time for when stop mode is woken up.
65 mb90650a series (1) register configuration address : 0000a1 h scm mcm ws1 ws0 scs mcs cs1 cs0 r r r/w r/w r/w r/w r/w r/w initial value 11111100 b clock selection register (ckscr) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 low-power consumption mode control register (lpmcr) address : 0000a0 h stp slp spl rst tmd cg1 cg0 w w r/w w w r/w r/w initial value 00011000 b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r w : readable and writable : read only : write only : unused
66 mb90650a series (2) block diagram low-power consumption control circuit and clock generator ckscr scm scs cs1 cs0 cg1 cg0 lpmcr mcm mcs ckscr ckscr slp stp lpmcr tmd ws1 ws0 spl lpmcr ckscr rst lpmcr internal reset generator pin high-impedance controller oscillation stabilization delay time selector 2 4 2 13 2 15 2 18 clock input timebase timer 2 12 2 14 2 16 2 19 pin hi-z rst pin internal rst to watchdog timer wdgrst interrupt request or rst sub osc stop main osc stop peripheral clock peripheral clock generation scm standby controller sleep mstp stop rst cancel cpu intermittent operation function cycle count selection circuit cpu clock selector 1/2 s pll multiplier circuit 2 134 sub clock sub clock divided by 4 (osc oscillation) main clock (osc oscillation) cpu clock cpu system clock generation 0/9/17/33 intermittent cycle selection internal data bus switching control
67 mb90650a series state transition diagram for clock selection (1) main scs = 1, mcs = 1 scm = 1, mcm = 1 cs1/0 = sub ? pll scs = 1, mcs = 0 scm = 0, mcm = 1 cs1/0 = main ? sub scs = 0, mcs = mcm = 1 scm = 1 main ? pll scs = 1, msc = 0 scm = 1, mcm = 1 cs1/0 = pll1 ? main scs = 0 or mcs = 0 scm = 1, mcm = 0 cs1/0 = 00 pll2 ? main scs = 0 or mcs = 1 scm = 1, mcm = 0 cs1/0 = 01 pll3 ? main scs = 0 or mcs = 1 scm = 1, mcm = 0 cs1/0 = 10 pll4 ? main scs = 0 or mcs = 1 scm = 1, mcm = 0 cs1/0 = 11 pll 1 multiplier scs = 1, msc = 0 scm = 1, mcm = 0 cs1/0 = 00 pll 2 multiplier scs = 1, msc = 0 scm = 1, mcm = 0 cs1/0 = 01 pll 3 multiplier scs = 1, msc = 0 scm = 1, mcm = 0 cs1/0 = 10 pll 4 multiplier scs = 1, msc = 0 scm = 1, mcm = 0 cs1/0 = 11 <1> <2> <3> <7> <7> <7> <7> <6> <6> <8> <8> <8> <8> <9> <6> <5> <6> <1> mcs bit cleared and scs bit set <2> pll clock oscillation stabilization delay complete and cs1/0 = 00 <3> pll clock oscillation stabilization delay complete and cs1/0 = 01 <4> pll clock oscillation stabilization delay complete and cs1/0 = 10 <5> pll clock oscillation stabilization delay complete and cs1/0 = 11 <6> mcs bit set or scs bit cleared <7> pll clock and main clock synchronized timing and scs = 1 <8> pll clock and main clock synchronized timing and scs = 0 <9> main clock oscillation stabilization delay complete and mcs = 0 power-on <4>
68 mb90650a series state transition diagam for clock selection (2) main scs = 1, mcs = 1 scm = 1 mcm = 1 pll ? sub scs = 0, mcs = scm = 1, mcm = 0 cs1/0 = main ? pll scs = 1, mcs = 0 scm = 1, mcm = 1 cs1/0 = main ? sub scs = 0 scm = 1 mcm = 1 sub ? main scs = 1 scm = 0 mcm = 1 sub scs = 0 scm = 0 mcm = 1 <1> <2> <3> <4> <5> <6> <1> scs bit cleared <2> sub clock edge detection timing <3> scs bit set <4> main clock oscillation stabilization delay complete and mcs = 1 <5> pll clock and main clock synchronized timing and scs = 0 <6> main clock ascillation stabilization delay complete and mcs = 0 power-on
69 mb90650a series 15. delayed interrupt generation module the delayed interrupt generation module is used to generate the task switching interrupt. interrupt requests to the f 2 mc-16l cpu can be generated and cleared by software using this module. (1) register details the dirr register controls generation and clearing of delayed interrupt requests. writing 1 to the register generates a delayed interrupt request. writing 0 to the register clears the delayed interrupt request. the register is set to the interrupt cleared state by a reset. either 0 or 1 can be written to the reserved bits. however, considering possible future extensions, it is recommended that the set bit and clear bit instructions are used for register access. (2) block diagram address : 00009f h r0 r/w initial value -------0 b delayed interrupt generation /release register (dirr) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w : readable and writable : unused delayed interrupt generation/release decoder interrupt latch internal data bus
70 mb90650a series 16. dtmf generator the dtmf (dual tone multifrequency) generator is a module that can generate a series of audio tones as heard from a push-button telephone or a radio transceiver with a keypad. it has the following features: capable of generating dtmf tones continuously (or even a single tone) capable of generating all ccitt tones: 0 to 9, *, #, a to d (1) register list (2) block diagram dtmf control register (dtmc) address : 000088 h csl2 csl1 csl0 cdis rdis oute r/w initial value 00000000 b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w dtmf data register (dtmd) address : 000089 h ddat3 ddat2 ddat1 r/w initial value 000x0000 b bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w : read/write enabled : unused x : undefined ddat0 r/w dtmf internal clock frequency divider row/col decoder preset counter dtmf data register (dtmd) clock pulse frequency select frequency select terminate control signal generator count clock col staircase generator row staircase generator dtmf control register (dtmc) internal bus voltage data adder frequency divider frequency select
71 mb90650a series n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0.0 v) (continued) parameter symbol value unit remarks min. max. power supply voltage v cc 1v ss C 0.3 v ss + 4.0 v mb90652a/653a/654a, mb90f654a v cc 2v ss C 0.3 v ss + 7.0 v v cc (v cc 1 = v cc 2) v ss C 0.3 v ss + 7.0 v mb90p653a av cc v ss C 0.3 v ss + 4.0 v mb90652a/653a/654a, mb90f654a *1 v ss C 0.3 v ss + 7.0 v mb90p653a *1 avrh avrl v ss C 0.3 v ss + 4.0 v mb90652a/653a/654a, mb90f654a v ss C 0.3 v ss + 7.0 v mb90p653a dvrh v ss C 0.3 v ss + 4.0 v mb90652a/653a/654a, mb90f654a v ss C 0.3 v ss + 7.0 v mb90p653a input voltage v i v ss C 0.3 v ss + 4.0 v mb90652a/653a/654a, mb90f654a *2 v ss C 0.3 v ss + 7.0 v mb90p653a *2,*6 output voltage v o v ss C 0.3 v ss + 4.0 v mb90652a/653a/654a, mb90f654a *2 v ss C 0.3 v ss + 7.0 v mb90p653a *2,*6 l level maximum output current i ol 10ma mb90652a/653a/654a, mb90f654a *3 15 ma mb90p653a *3 l level average output current i olav 3ma mb90652a/653a/654a, mb90f654a *4 4 ma mb90p653a *4 l level total maximum output current s i ol 60ma mb90652a/653a/654a, mb90f654a 100 ma mb90p653a l level total average output current s i olav 30ma mb90652a/653a/654a, mb90f654a *5 50 ma mb90p653a *5 h level maximum output current i oh C10 ma mb90652a/653a/654a, mb90f654a *3 C15 ma mb90p653a *3
72 mb90650a series (continued) (v ss = av ss = 0.0 v) *1: av cc , avrh, avrl and dvrh must not exceed v cc (v cc1 and v cc2 are contained) . similarly, avrl must not exceed avrh. *2: v i and v o must not exceed v cc (v cc1 and v cc2 are contained) + 0.3 v. *3: maximum output current specifies the peak value or one corresponding pin. *4: the average output current is the rating for the current from an individual pin averaged over 100 ms. *5: the average total output current is the rating for the current from all pins averaged over 100 ms. *6: applies to the p47 and p70 to p72 on the mb90652a/653a/654a and mb90f654a. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. h level average output current i ohav C3ma mb90652a/653a/654a, mb90f654a *4 C4 ma mb90p653a *4 h level total maximum output current s i oh C60 ma mb90652a/653a/654a, mb90f654a C100 ma mb90p653a h level total average output current s i ohav C30 ma *5 power consumption p d 200 mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
73 mb90650a series 2. recommended operating conditions (v ss = av ss = 0.0 v) note: i 2 c must be used at above 2.7 v. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min. max. power supply voltage v cc 1 2.2 3.6 v for normal operation (mb90652a/653a/654a) 2.7 3.6 v for normal operation (mb90p653a) 2.4 3.6 v for normal operation (mb90f654a) v cc 2 2.2 5.5 v for normal operation (mb90652a/653a/654a) 2.7 5.5 v for normal operation (mb90p653a) 2.4 5.5 v for normal operation (mb90f654a) v cc 1 1.8 3.6 v to maintain statuses in stop mode (mb90652a/653a/654a) 1.8 5.5 v to maintain statuses in stop mode (mb90p653a) 1.8 3.6 v to maintain statuses in stop mode (mb90f654a) v cc 2 1.8 5.5 v to maintain statuses in stop mode (mb90652a/653a/654a) 1.8 5.5 v to maintain statuses in stop mode (mb90p653a) 1.8 5.5 v to maintain statuses in stop mode (mb90f654a) h level input voltage v ih 0.7 v cc v cc + 0.3 v pins other than v ihs and v ihm v ihs 0.8 v cc v cc + 0.3 v hysteresis input pins v ihm v cc C 0.3 v cc + 0.3 v md pin input v iht 2.4 v cc + 0.3 v ttl input pins l level input voltage v il v ss C 0.3 0.3 v cc v pins other than v ils and v ilm v ils v ss C 0.3 0.2 v cc v hysteresis input pins v ilm v ss C 0.3 v ss + 0.3 v md pin input v ilt v ss C 0.3 0.8 v ttl input pins operating temperature t a C40 +85 c
74 mb90650a series 3. dc characteristics (mb90652a/653a/654a: v cc = 2.2 v to 3.6 v, v ss = 0.0 v, t a = C40c to +85c) (mb90p653a: v cc = 2.7 v to 3.3 v, v ss = 0.0 v, t a = C40c to +85c) (mb92f654a: v cc = 2.4 v to 3.6 v, v ss = 0.0 v, t a = C40c to +85c) * 1 : p40 to p46 are n-ch open-drain pins to be controlled and are usually used as cmos devices. * 2 : when the device is used with dual power supplies, the p20 to p27, p30 to p37, p40 to p47, and p70 to p72 are the 5 v pins and the rest are the 3 v pins. (continued) parameter symbol pin name condition value unit remarks min. typ. max. h level output voltage*2 v oh pins except p47, p70 to p72 v cc 2 = 4.5 v, i oh = C4.0 ma v cc 2C 0.5 v when the 5-v power supply is used v cc = 2.7 v, i oh = C1.6 ma v cc 1C 0.3 v when the 3-v power supply is used *1 l level output voltage*2 v ol all output pins v cc 2 = 4.5 v, i ol = 4.0 ma 0.4v when the 5-v power supply is used v cc = 2.7 v, i ol = 2.0 ma 0.4v when the 3-v power supply is used input leakage current i il except p50 to p57, p90, p91 v cc = 3.3 v, v ss < v i < v cc C10 10 m a pull-up resistor rpull when v cc = 3.0 v, t a = +25 c 40 80 400 k w mb90p653a 20 65 200 k w mb90652a/653a/654a, mb90f654a open-drain output leakage current i leak p40 to p47, p70 to p72 0.110 m a power supply current i cc when v cc = 3.0 v internal 8 mhz operation 1020ma mb90652a/653a/654a: during normal operation i cc 1724ma mb90652a/653a/654a: in a/d operation i cc 1926ma mb90652a/653a/654a: in d/a operation i ccs 2.55ma mb90652a/653a/654a: during sleep i cc when v cc = 3.0 v internal 8 mhz operation 2027ma mb90p653a: during normal operation i cc 2431ma mb90p653a: in a/d operation i cc 2633ma mb90p653a: in d/a operation i ccs 4.210ma mb90p653a: during sleep
75 mb90650a series (continued) (mb90652a/653a/654a: v cc = 2.2 v to 3.6 v, v ss = 0.0 v, t a = C40c to +85c) (mb90p653a: v cc = 2.7 v to 3.3 v, v ss = 0.0 v, t a = C40c to +85c) (mb90f654a: v cc = 2.4 v to 3.6 v, v ss = 0.0 v, t a = C40c to +85c) note: v cc = v cc 1 = v cc 2 parameter symbol pin name condition value unit remarks min. typ. max. power supply current i cc when v cc = 3.0 v internal 16 mhz operation 2035ma mb90652a/653a/654a: during normal operation i cc 2745ma mb90f654a: during normal operation i cc 3350ma mb90f654a: flash write/erase i cc 3141ma mb90652a/653a/654a: in a/d operation i cc 3442ma mb90652a/653a/654a: in d/a operation i ccs when v cc = 3.0 v internal 16 mhz operation 4.810ma mb90652a/653a/654a: during sleep i ccs 6.212ma mb90f654a: during sleep i cch t a = +25c when v cc = 3.0 v 0.120 m a mb90652a/653a/654a: during stop i cch 0.240 m a mb90f654a: during stop i ccl v cc = 3.0 v, t a = +25c external 32 khz operation (internal 8 mhz operation) 16 140 m a mb90652a/653a/654a, mb90f654a: in sub operation i ccl 4.46ma mb90p653a: in sub operation i cct v cc = 3.0 v, t a = +25c external 32 khz operation 1030 m a mb90652a/653a/654a: in watch mode i cct 1530 m a mb90f654a: in watch mode i cct 1560 m a mb90p653a: in watch mode input capacitance c in except av cc , av ss , v cc , v ss 10 80 pf
76 mb90650a series 4. ac characteristics (1) clock timing (v cc = 2.7 v to 3.3 v, v ss = 0.0 v, t a = C40 c to +85 c) *1: the frequency fluction ratio indicates the maximum fluctuation ratio from the set center frequency while locked when using the pll multiplier. because the pll frequency fluctuates around the set frequency with a certain cycle [approximately clk (1 cyc to 50 cyc)], the worst value is not maintained for long. (the pulse, if featured with the long period, would produce practically no error.) *2: the duty ratio should be in the range 30% to 70%. note: v cc = v cc 1 = v cc 2 parameter symbol pin name condition value unit remarks min. typ. max. clock frequency f ch x0, x1 332mhz mb90652a/653a/ 654a,mb90f654a 3 16 mhz mb90p653a f cl x0a, x1a 32.768 khz clock cycle time t c x0, x1 31.25 333 ns mb90652a/653a/ 654a,mb90f654a 62.5 333 ns mb90p653a t cl x0a, x1a 30.5 m s input clock pulse width p wh p wl x0 5ns mb90652a/653a/ 654a,mb90f654a *2 10 ns mb90p653a *2 p wlh p wll x0a 15.2 m s*2 input clock rise time and fall time t cr t cf x0 5 ns external clock internal operating clock frequency f cp 1.516mhz mb90652a/653a/ 654a,mb90f654a 1.5 8 mhz mb90p653a f cpl 8.192khz internal operating clock cycle time t cp 62.5 666 ns t cpl 122.1 m s frequency fluctuation ratio d f 5 % when locked *1 + center frequency + a a f o d f = a f o 100 (%)
77 mb90650a series main clock timing condition (x0 , x1) 0.8 v cc 0.2 v cc t cf t cr t c p wh x0 p wl subclock timing condition (x0a , x1a ) 0.8 v cc 0.2 v cc t cl p whl x0a p wll
78 mb90650a series pll operation assurance range 3.6 2.7 2.2 516 power supply voltage (v cc ) normal operation range 2.5 3 1 internal clock (f cp ) 34 8 16 24 32 16 12 9 8 4 multiply by 4 multiply by 3 no multiplier oscillation clock (f c ) internal clock (f cp ) relationship between the oscillation frequency and internal operating clock frequency relationship between the internal operating clock frequency and power supply voltage (mb90652a/653a/654a, mb90f654a) multiply by 1 (v) (mhz) pll operation assurance range 3.6 2.7 38 power supply voltage (v cc ) normal operation range 1.5 internal clock (f cp ) relationship between the internal oprating clock frequency and power supply voltage (mb90p653a) (v) (mhz) pll operation assurance range (mhz) (mhz) multiply by 2
79 mb90650a series the ac characteristics are for the following measurement reference voltages. input signal waveform output signal waveform hysteresis input pins 0.8 v cc 0.2 v cc other than hysteresis or md input pins 0.7 v cc 0.3 v cc output pins 2.4 v 0.2 v
80 mb90650a series (2) clock output timing (v cc = 2.7 v to 3.3 v, v ss = 0.0 v, t a = C40 c to +85 c) t cp : see (1) clock timing. note: v cc = v cc 1 = v cc 2 (3) reset input specifications (v cc = 2.7 v to 3.3 v, v ss = 0.0 v, t a = C40 c to +85 c) t cp : see (1) clock timing. note: v cc = v cc 1 = v cc 2 parameter symbol pin name condition value unit remarks min. max. cycle time t cyc clk t cp ns clk - ? clk t chcl clk v cc = 3.0 v 10% t cp / 2 C 20 t cp / 2 + 20 ns t cp / 2 C 64 t cp / 2 + 64 ns in the external frequency of 5 mhz parameter symbol pin name condition value unit remarks min. max. reset input time t rstl rst 16 t cp ns t cyc t chcl clk 0.8 v 2.4 v 2.4 v 0.2 v cc 0.2 v cc rst t rstl ac characteristics measurement conditions c l pin clk, ale: c l = 30 pf ad15 to ad00 (address/data bus), rd, wr: c l = 80 pf c l : load capacitance at testing
81 mb90650a series (4) power on supply specifications (power-on reset) (v cc = 2.7 v to 3.3 v, v ss = 0.0 v, t a = C40 c to +85 c) * : when the power rising, v cc must be less than 0.2 v. notes: the above standards are the values needed in order to activate a power-on reset. activate a power-on reset by turning on the power supply again this in device. v cc = v cc 1 = v cc 2 parameter symbol pin name condition value unit remarks min. max. power supply rising time t r v cc 30ms* power supply cut-off time t off v cc 1ms due to repeat operation holding ram data 2.7 v t r 0.2 v v cc main power supply voltage sub-power supply voltage v ss v cc it is recommended that the rate of increase in the voltage be kept to no more than 50 mv/ms. abrupt changes in the power supply voltage may cause a power-on reset. when changing the power supply voltage during operation, suppress variations in the voltage and ensure that the voltage rises smoothly, as shown in the following figure. t off
82 mb90650a series (5) bus read timing (v cc = 2.7 v to 3.3 v, v ss = 0.0 v, t a = C40 c to +85 c) t cp : see (1) clock timing. note: v cc = v cc 1 = v cc 2 parameter symbol pin name condition value unit remarks min. max. ale pulse width t lhll ale t cp /2 C 20 ns mask/flash t cp / 2 C 35 ns mb90p653a valid address ? ale time t avll multiplexed address t cp / 2 C 25 ns mask/flash t cp / 2 C 40 ns mb90p653a ale ? address valid time t llax multiplexed address t cp / 2 C 15 ns valid address ? rd time t avrl multiplexed address t cp C 15 ns valid address ? valid data input t avdv multiplexed address 5 t cp / 2 C 60 ns mask/flash 5 t cp / 2 C 80 ns mb90p653a rd pulse width t rlrh rd 3 t cp / 2 C 20 ns rd ? valid data input t rldv d15 to d00 5 t cp / 2 C 60 ns mask/flash 5 t cp / 2 C 80 ns mb90p653a rd - ? data hold time t rhdx d15 to d00 0 ns rd - ? ale - time t rhlh rd , ale t cp / 2 C 15 ns rd - ? address valid time t rhax address, rd t cp / 2 C 10 ns valid address ? clk - time t avch address, clk t cp / 2 C20 ns rd ? clk - time t rlch rd , clk t cp / 2 C 20 ns
83 mb90650a series clk ale rd t rhdx 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc a23 to a16 d15 to d00 t avch t rlch t avll t llax t lhll t avrl t rlrh t avdv t rldv t rhax t rhlh address read data
84 mb90650a series (6) bus write timing (v cc = 2.7 v to 3.3 v, v ss = 0.0 v, t a = C40 c to +85 c) t cp : see (1) clock timing. note: v cc = v cc 1 = v cc 2 parameter symbol pin name condition value unit remarks min. max. valid address ? wr time t avwl a23 to a00 t cp C 15 ns wr pulse width t wlwh wr 3 t cp / 2 C 20 ns valid data output ? wr - time t dvwh d15 to d00 3 t cp / 2 C 20 ns wr - ? data hold time t whdx d15 to d00 20 ns mask/flash 30 ns mb90p653a wr - ? address valid time t whax a23 to a00 t cp / 2 C 10 ns wr - ? ale - time t whlh wr , ale t cp / 2 C 15 ns wr ? clk - time t wlch wr , ale t cp / 2 C 20 ns clk ale wr (wrl, wrh) 0.8 v 2.4 v a23 to a16 d15 to d00 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v t wlch t whlh t avwl t wlwh t whax t dvwh t whdx address write data
85 mb90650a series (7) ready input timing (v cc = 2.7 v to 3.3 v, v ss = 0.0 v, t a = C40 c to +85 c) notes: use the auto-ready function if the rdy setup time is too short v cc = v cc 1 = v cc 2. parameter symbol pin name condition value unit remarks min. max. rdy setup time t ryhs rdy 45 ns mask/flash 70 ns mb90p653a rdy hold time t ryhh rdy 0 ns clk ale rd/wr rdy (when one wait states are inserted) rdy (when wait states are not inserted) 2.4 v 2.4 v 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t ryhh t ryhs t ryhs
86 mb90650a series (8) hold timing (v cc = 2.7 v to 3.3 v, v ss = 0.0 v, t a = C40 c to +85 c) t cp : see (1) clock timing. notes: after reading hrq, more than one cycle is required before changing hak . v cc = v cc 1 = v cc 2 parameter symbol pin name condition value unit remarks min. max. pin floating ? hak time t xhal hak 30t cp ns hak - ? pin valid time t hahv hak t cp 2 t cp ns hak t xhal t hahv pin high impedance 0.8 v 2.4 v
87 mb90650a series (9) uart timing (v cc = 2.7 v to 3.3 v, v ss = 0.0 v, t a = C40 c to +85 c) notes: ? these are the ac characteristics for clk synchronous mode. ?c l is the load capacitance connected to the pin at testing. ?t cp is the machine cycle period (unit: ns). ?v cc = v cc 1 = v cc 2 parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc c l = 80 pf + 1 ttl for the internal shift clock mode output pin 8 t cp ns sck ? sot delay time t slov C80 80 ns mask/flash C120 120 ns mb90p653a valid sin ? sck - t ivsh 100 ns mask/flash 200 ns mb90p653a sck - ? valid sin hold time t shix t cp ns serial clock h pulse width t shsl c l = 80 pf + 1 ttl for the external shift clock mode output pin 4 t cp ns serial clock l pulse width t slsh 4 t cp ns sck ? sot delay time t slov 150 ns mask/flash 200 ns mb90p653a valid sin ? sck - t ivsh 60 ns mask/flash 120 ns mb90p653a sck - ? valid sin hold time t shix 60 ns mask/flash 120 ns mb90p653a
88 mb90650a series internal shift clock mode external shift clock mode sck sot sin t scyc t slov t ivsh t shix 2.4 v 0.8 v cc 0.8 v 0.8 v 2.4 v 0.8 v 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin t slsh t slov t ivsh t shix t shsl 0.8 v cc 2.4 v 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc
89 mb90650a series (10) i/o extended serial timing (v cc = 2.7 v to 3.3 v, v ss = 0.0 v, t a = C40 c to +85 c) notes: ? these are the ac characteristics for clk synchronous mode. ?c l is the load capacitance connected to the pin at testing. ?t cp is the machine cycle period (unit: ns). ? the values in the table are target values. ?v cc = v cc 1 = v cc 2 parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc c l = 80 pf + 1 ttl for the internal shift clock mode output pin 8 t cp ns sck ? sot delay time t slov 80 ns mask/flash 160 ns mb90p653a valid sin ? sck - t ivsh t cp ns sck - ? valid sin hold time t shix t cp ns serial clock h pulse width t shsl c l = 80 pf + 1 ttl for the external shift clock mode output pin 230 ns mask/flash 460 ns mb90p653a serial clock l pulse width t slsh 230 ns mask/flash 460 ns mb90p653a sck ? sot delay time t slov 2 t cp ns valid sin ? sck - t ivsh t cp ns sck - ? valid sin hold time t shix 2 t cp ns
90 mb90650a series internal shift clock mode external shift clock mode sck sot sin t scyc t slov t ivsh t shix 2.4 v 0.8 v cc 0.8 v 0.8 v 2.4 v 0.8 v 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin t slsh t slov t ivsh t shix t shsl 0.8 v cc 2.4 v 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc
91 mb90650a series (11) i 2 c timing (v cc = 2.7 v to 3.3 v, v ss = 0.0 v, t a = C40 c to +85 c) note: v cc = v cc 1 = v cc 2 parameter symbol pin name condition value unit remarks min. max. scl clock frequency f scl 0 100 khz bus free time between stop and start conditions t bus 4.7 m s hold time (re-send) start t hdsta 4.0 m s the first clock pulse is generated after this period. scl clock l state hold time t low 4.7 m s scl clock h state hold time t high 4.0 m s re-send start condition setup time t susta 4.7 m s data hold time t hddat 0 m s data setup time t sudat 40ns sda and scl signal rising time t r 1000ns sda and scl signal falling time t f 300 ns stop condition setup time t susto 4.0 m s t low t r t f t hdsta t hddat t high t sudat t susta t hdsta t susto 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc sda scl t bus
92 mb90650a series 5. a/d converter electrical characteristics (mb90652a/653a/654a: v cc = 2.2 v to 3.3v, v ss = av ss =0.0v, 2.7 v avrh C avrl, t a = C40 c to +85 c) (mb90f654a: v cc = 2.4 v to 3.6 v, v ss = av ss = 0.0 v, 2.7 v avrh C avrl, t a = C40 c to +85 c) (mb90p653a: v cc = 2.7 v to 3.3 v, v ss = av ss = 0.0 v, 2.7 v avrh C avrl, t a = C40 c to +85 c) *1: for a 16 mhz machine clock *2: for an 8 mhz machine clock *3: the current when the a/d converter is not operating or the cpu is in stop mode (for v cc = av cc = avrh = 3.0 v). notes: ? the error increases proportionally as |avrh C avrl| decreases. ? the output impedance of the external circuits connected to the analog inputs should be in the following range. the output impedance of the external circuit should be less than approximately 7 k w. when using an external capacitor, it is recommended to have several thousand times the capacitance of the internal capacitor as a guid, if one takes into consideration the effect of the divided capacitance between the external capacitor and the internal capacitor. ? if the output impedance of the external circuit is too high, the sampling time might be insufficient (sampling time = 3.75 m s at a machine clock of 16 mhz). ?v cc = v cc 1 = v cc 2 (continued) parameter symbol pin name value unit remarks min. typ. max. resolution 10 10 bit total error 3.0 lsb linearity error 2.0 lsb differential linearity error 1.9 lsb mask/flash 1.5 lsb mb90p653a zero transition voltage v ot an0 to an7 avrl C 1.5 lsb avrl + 0.5 lsb avrl + 2.5 lsb mv full scale transition voltage v fst an0 to an7 avrh C 4.5 lsb avrh C 1.5 lsb avrh + 0.5 lsb mv conversion time 6.125 *1 m s mask/flash 12.25 *2 m s mb90p653a analog port input current i ain an0 to an7 0.1 10 m a analog input voltage v ain an0 to an7 avrl avrh v reference voltage avrh avrl + 2.7 av cc v avrl 0 avrh C 2.7 v power supply current i a av cc 3ma i ah av cc 5 *3 m a reference voltage supply current i r avrh 200 m a i rh avrh 5 *3 m a variation between channels an0 to an7 4 lsb
93 mb90650a series (continued) r on1 r on2 r on3 c 1 c 0 r on4 analog input sample hold circuit comparator analog input circuit model diagram r on1 : approx. 5 k w r on2 : approx. 617 w r on3 : approx. 617 w r on4 : approx. 473 w c 0 : approx. 35 pf c 1 : approx. 2 pf note: use the values shown as guids only.
94 mb90650a series 6. d/a converter electrical characteristics (mb90652a/653a : v cc = 2.2 v to 3.3 v, v ss = dv ss = 0.0 v, 2.2 v dvrh C dv ss , t a = C40 c to +85 c) (mb90f654a : v cc = 2.4 v to 3.6 v, v ss = dv ss = 0.0 v, 2.4 v dvrh C dv ss , t a = C40 c to +85 c) (mb90p653a : v cc = 2.7 v to 3.3 v, v ss = dv ss = 0.0 v, 2.7 v dvrh C dv ss , t a = C40 c to +85 c) *1: conversion time is the value at the load capacitance = 20 pf. *2: dvrh C dv ss (av ss ) *3: current value at conversion *4: current value when stopped note: v cc = v cc 1 = v cc 2 parameter symbol pin name value unit remarks min. typ. max. resolution 8 8 bit differential linearity error 0.9 lsb absolute accuracy 1% linearity error 1.5 lsb conversion time 10.0 20.0 m s*1 analog reference power supply voltage dvrh 2.2 v cc v mb90652a/653a/654a*2 2.4 v cc v mb90f654a *2 2.7 v cc v mb90p653a *2 reference voltage supply current i dvr dvrh 100 m a*3 i dvrs 5 m a*4 analog output impedance 28 k w
95 mb90650a series 7. dtmf electrical characteristics (mb90652a/653a : v cc = 2.2 v to 3.3 v, v ss = dv ss = 0.0 v, 2.2 v dvrh C dv ss , t a = C40 c to +85 c) (mb90f654a : v cc = 2.4 v to 3.6 v, v ss = dv ss = 0.0 v, 2.4 v dvrh C dv ss , t a = C40 c to +85 c) (mb90p653a : v cc = 2.7 v to 3.3 v, v ss = dv ss = 0.0 v, 2.7 v dvrh C dv ss , t a = C40 c to +85 c) note: v cc =v cc 1 = v cc 2 parameter symbol condition value unit remarks min. typ. max. output load condition r o v cc = 3 v t a = 25 c machine clock f = 16 mhz 30 k w to be specified with dtmf pin pull-down resistor dtmf output offset voltage (at signal output) v mof 0.4 v when dtmf terminal is opened r o = 200 k w dtmf output amplitude (col single tone) v mfc 450 530 600 mv p-p dtmf output amplitude (row single tone) v mfor 330 440 500 mv p-p col/row level difference r mf 1.6 2.0 2.4 db v cc v ss x0 x1 r o dtmf - 48 db / oct audio analizer ? output level measurement circuit output level low-pass filter 16mhz
96 mb90650a series n example characteristics v ihs : threshold when input voltage in hysteresis characteristics is set to h level v ils : threshold when input voltage in hysteresis characteristics is set to l level v ih : threshold when input voltage is set to h level v il : threshold when input voltage is set to l level (1) h level output voltage (2) l level output voltage 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 ? ? ? ? ? v cc = 2.4 v v cc = 2.5 v v cc = 2.7 v v cc = 3.0 v v cc = 3.3 v v cc = 3.6 v v oh vs. i oh t a = +25 c i oh (ma) v oh (v) v cc = 2.4 v v cc = 2.5 v v cc = 2.7 v v cc = 3.0 v v cc = 3.3 v v cc = 3.6 v t a = +25 c i ol (ma) v ol vs. i ol v ol (v) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 12345 v in vs. v cc t a = +25 c v cc (v) v in (v) v ih v il 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 2.4 2.7 3.0 3.3 3.6 v in vs. v cc t a = +25 c v cc (v) v in (v) v ihs v ils 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 2.4 2.7 3.0 3.3 3.6 (3) h level input voltage/l level input voltage (coms input) (4) h level input voltage/l level input voltage (hysteresis input)
97 mb90650a series (5) power supply current (f cp = internal operating clock frequency) ? mask rom products i cc vs. v cc t a = +25 c v cc (v) i cc (ma) f cp = 16 mh z f cp = 10 mh z f cp = 8 mh z f cp = 5 mh z 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 2.4 2.7 3 3.3 3.6 i ccs vs. v cc t a = +25 c v cc (v) i ccs (ma) f cp = 16 mh z f cp = 10 mh z f cp = 8 mh z f cp = 5 mh z 10 9 8 7 6 5 4 3 2 1 0 2.4 2.7 3 3.3 3.6 i cch vs. v cc t a = +25 c v cc (v) i cch ( m a) 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 2.4 2.7 3 3.3 3.6 i a vs. a v cc t a = +25 c av cc (v) i a (ma) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.4 2.7 3 3.3 3.6 i ccl vs. v cc t a = +25 c v cc (v) i ccl ( m a) 50 45 40 35 30 25 20 15 10 5 0 2.4 2.7 3 3.3 3.6 i r vs. a v cc t a = +25 c av cc (v) i r (ma) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.4 2.7 3 3.3 3.6
98 mb90650a series ? otprom products i cc vs. v cc t a = +25 c v cc (v) i cc (ma) f cp = 16 mh z f cp = 10 mh z f cp = 8 mh z f cp = 5 mh z 60 55 50 45 40 35 30 25 20 15 10 5 0 2.4 2.7 3 3.3 3.6 i ccl vs. v cc t a = +25 c v cc (v) i ccl (ma) 10 9 8 7 6 5 4 3 2 1 0 2.4 2.7 3 3.3 3.6 i ccs vs. v cc t a = +25 c v cc (v) i ccs (ma) f cp = 16 mh z f cp = 10 mh z f cp = 8 mh z f cp = 5 mh z 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2.4 2.7 3 3.3 3.6 i cch vs. v cc t a = +25 c v cc (v) i cch ( m a) 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.4 2.7 3 3.3 3.6
99 mb90650a series ? flah products i cc vs. v cc v cc (v) i cc (ma) f cp = 16 mh z f cp = 10 mh z f cp = 8 mh z f cp = 5 mh z 2.4 2.7 3 3.3 3.6 i ccs vs. v cc t a = + 25 c v cc (v) i ccs (ma) f cp = 16 mh z f cp = 10 mh z f cp = 8 mh z f cp = 5 mh z 10 9 8 7 6 5 4 3 2 1 0 2.4 2.7 3 3.3 3.6 i cch vs. v cc v cc (v) i cch ( m a) 2.4 2.7 3 3.3 3.6 i ccl vs. v cc t a = + 25 c v cc (v) i ccl ( m a) 50 45 40 35 30 25 20 15 10 5 0 2.4 2.7 3 3.3 3.6 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 t a = + 25 c 0.80 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 t a = + 25 c
100 mb90650a series (6) pull-up resistance ? mask rom products ? otprom products ? flash products r vs. v cc v cc (v) r (k w ) 2.4 3 2.7 3.3 3.6 1000 100 10 t a = +25 c r vs. v cc v cc (v) r (k w ) 2.4 3 2.7 3.3 3.6 1000 100 10 t a = +25 c r vs. v cc v cc (v) r (k w ) 2.4 3 2.7 3.3 3.6 1000 100 10 t a = + 25 c
101 mb90650a series n instructions (340 instructions) table 1 explanation of items in tables of instructions item meaning mnemonic upper-case letters and symbols: represented as they appear in assembler. lower-case letters: replaced when described in assembler. numbers after lower-case letters: indicate the bit width within the instruction. # indicates the number of bytes. ~ indicates the number of cycles. m : when branching n : when not branching see table 4 for details about meanings of other letters in items. rg indicates the number of accesses to the register during execution of the instruction. it is used calculate a correction value for intermittent operation of cpu. b indicates the correction value for calculating the number of actual cycles during execution of the instruction. (table 5) the number of actual cycles during execution of the instruction is the correction value summed with the value in the ~ column. operation indicates the operation of instruction. lh indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. z : transfers 0. x : extends with a sign before transferring. C : transfers nothing. ah indicates special operations involving the upper 16 bits in the accumulator. * : transfers from al to ah. C : no transfer. z : transfers 00 h to ah. x : transfers 00 h or ff h to ah by signing and extending al. i indicates the status of each of the following flags: i (interrupt enable), s (stack), t (sticky bit), n (negative), z (zero), v (overflow), and c (carry). * : changes due to execution of instruction. C : no change. s : set by execution of instruction. r : reset by execution of instruction. s t n z v c rmw indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : instruction is a read-modify-write instruction. C : instruction is not a read-modify-write instruction. note: a read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.
102 mb90650a series table 2 explanation of symbols in tables of instructions (continued) symbol meaning a 32-bit accumulator the bit length varies according to the instruction. byte : lower 8 bits of al word : 16 bits of al long : 32 bits of al:ah ah al upper 16 bits of a lower 16 bits of a sp stack pointer (usp or ssp) pc program counter pcb program bank register dtb data bank register adb additional data bank register ssb system stack bank register usb user stack bank register spb current stack bank register (ssb or usb) dpr direct page register brg1 dtb, adb, ssb, usb, dpr, pcb, spb brg2 dtb, adb, ssb, usb, dpr, spb ri r0, r1, r2, r3, r4, r5, r6, r7 rwi rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 rwj rw0, rw1, rw2, rw3 rli rl0, rl1, rl2, rl3 dir compact direct addressing addr16 addr24 ad24 0 to 15 ad24 16 to 23 direct addressing physical direct addressing bit 0 to bit 15 of addr24 bit 16 to bit 23 of addr24 io i/o area (000000 h to 0000ff h ) imm4 imm8 imm16 imm32 ext (imm8) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data disp8 disp16 8-bit displacement 16-bit displacement bp bit offset vct4 vct8 vector number (0 to 15) vector number (0 to 255) ( )b bit address
103 mb90650a series (continued) table 3 effective address fields note: the number of bytes in the address extension is indicated by the + symbol in the # (number of bytes) column in the tables of instructions. symbol meaning rel branch specification relative to pc ear eam effective addressing (codes 00 to 07) effective addressing (codes 08 to 1f) rlst register list code notation address format number of bytes in address extension * 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rl1) rl2 (rl2) rl3 (rl3) register direct ea corresponds to byte, word, and long-word types, starting from the left 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect 0 0c 0d 0e 0f @rw0 + @rw1 + @rw2 + @rw3 + register indirect with post-increment 0 10 11 12 13 14 15 16 17 @rw0 + disp8 @rw1 + disp8 @rw2 + disp8 @rw3 + disp8 @rw4 + disp8 @rw5 + disp8 @rw6 + disp8 @rw7 + disp8 register indirect with 8-bit displacement 1 18 19 1a 1b @rw0 + disp16 @rw1 + disp16 @rw2 + disp16 @rw3 + disp16 register indirect with 16-bit displacement 2 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address 0 0 2 2
104 mb90650a series table 4 number of execution cycles for each type of addressing note: (a) is used in the ~ (number of states) column and column b (correction value) in the tables of instructions. table 5 correction values for number of cycles used to calculate number of actual cycles notes: (b), (c), and (d) are used in the ~ (number of states) column and column b (correction value) in the tables of instructions. when the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. table 6 correction values for number of cycles used to calculate number of program fetch cycles notes: when the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for worst case calculations. code operand (a) number of register accesses for each type of addressing number of execution cycles for each type of addressing 00 to 07 ri rwi rli listed in tables of instructions listed in tables of instructions 08 to 0b @rwj 2 1 0c to 0f @rwj + 4 2 10 to 17 @rwi + disp8 2 1 18 to 1b @rwj + disp16 2 1 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 4 4 2 1 2 2 0 0 operand (b) byte (c) word (d) long number of cycles number of access number of cycles number of access number of cycles number of access internal register +01+01+02 internal memory even address internal memory odd address +0 +0 1 1 +0 +2 1 2 +0 +4 2 4 even address on external data bus (16 bits) odd address on external data bus (16 bits) +1 +1 1 1 +1 +4 1 2 +2 +8 2 4 external data bus (8 bits) +11+42+84 instruction byte boundary word boundary internal memory +2 external data bus (16 bits) +3 external data bus (8 bits) +3
105 mb90650a series table 7 transfer instructions (byte) [41 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw mov a, dir mov a, addr16 mov a, ri mov a, ear mov a, eam mov a, io mov a, #imm8 mov a, @a mov a, @rli+disp8 movn a, #imm4 movx a, dir movx a, addr16 movx a, ri movx a, ear movx a, eam movx a, io movx a, #imm8 movx a, @a movx a,@rwi+disp8 movx a, @rli+disp8 mov dir, a mov addr16, a mov ri, a mov ear, a mov eam, a mov io, a mov @rli+disp8, a mov ri, ear mov ri, eam mov ear, ri mov eam, ri mov ri, #imm8 mov io, #imm8 mov dir, #imm8 mov ear, #imm8 mov eam, #imm8 mov @al, ah xch a, ear xch a, eam xch ri, ear xch ri, eam 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ 3 4 2 2 3+ (a) 3 2 3 10 1 3 4 2 2 3+ (a) 3 2 3 5 10 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 (b) 0 2 (b) byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rli)+disp8) byte (a) ? imm4 byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rwi)+disp8) byte (a) ? ((rli)+disp8) byte (dir) ? (a) byte (addr16) ? (a) byte (ri) ? (a) byte (ear) ? (a) byte (eam) ? (a) byte (io) ? (a) byte ((rli) +disp8) ? (a) byte (ri) ? (ear) byte (ri) ? (eam) byte (ear) ? (ri) byte (eam) ? (ri) byte (ri) ? imm8 byte (io) ? imm8 byte (dir) ? imm8 byte (ear) ? imm8 byte (eam) ? imm8 byte ((a)) ? (ah) byte (a) ? (ear) byte (a) ? (eam) byte (ri) ? (ear) byte (ri) ? (eam) z z z z z z z z z z x x x x x x x x x x C C C C C C C C C C C C C C C C C z z C C * * * * * * * C * * * * * * * * * C * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * r * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
106 mb90650a series table 8 transfer instructions (word/long word) [38 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw movw a, dir movw a, addr16 movw a, sp movw a, rwi movw a, ear movw a, eam movw a, io movw a, @a movw a, #imm16 movw a, @rwi+disp8 movw a, @rli+disp8 movw dir, a movw addr16, a movw sp, a movw rwi, a movw ear, a movw eam, a movw io, a movw @rwi+disp8, a movw @rli+disp8, a movw rwi, ear movw rwi, eam movw ear, rwi movw eam, rwi movw rwi, #imm16 movw io, #imm16 movw ear, #imm16 movw eam, #imm16 movw @al, ah xchw a, ear xchw a, eam xchw rwi, ear xchw rwi, eam 2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 3 4 1 2 2 3+ (a) 3 3 2 5 10 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c) 0 2 (c) 0 2 (c) word (a) ? (dir) word (a) ? (addr16) word (a) ? (sp) word (a) ? (rwi) word (a) ? (ear) word (a) ? (eam) word (a) ? (io) word (a) ? ((a)) word (a) ? imm16 word (a) ? ((rwi) +disp8) word (a) ? ((rli) +disp8) word (dir) ? (a) word (addr16) ? (a) word (sp) ? (a) word (rwi) ? (a) word (ear) ? (a) word (eam) ? (a) word (io) ? (a) word ((rwi) +disp8) ? (a) word ((rli) +disp8) ? (a) word (rwi) ? (ear) word (rwi) ? (eam) word (ear) ? (rwi) word (eam) ? (rwi) word (rwi) ? imm16 word (io) ? imm16 word (ear) ? imm16 word (eam) ? imm16 word ((a)) ? (ah) word (a) ? (ear) word (a) ? (eam) word (rwi) ? (ear) word (rwi) ? (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C movl a, ear movl a, eam movl a, #imm32 movl ear, a movl eam, a 2 2+ 5 2 2+ 4 5+ (a) 3 4 5+ (a) 2 0 0 2 0 0 (d) 0 0 (d) long (a) ? (ear) long (a) ? (eam) long (a) ? imm32 long (ear) ? (a) long (eam) ? (a) C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * C C C C C C C C C C C C C C C
107 mb90650a series table 9 addition and subtraction instructions (byte/word/long word) [42 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw add a,#imm8 add a, dir add a, ear add a, eam add ear, a add eam, a addc a addc a, ear addc a, eam adddc a sub a, #imm8 sub a, dir sub a, ear sub a, eam sub ear, a sub eam, a subc a subc a, ear subc a, eam subdc a 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 byte (a) ? (a) +imm8 byte (a) ? (a) +(dir) byte (a) ? (a) +(ear) byte (a) ? (a) +(eam) byte (ear) ? (ear) + (a) byte (eam) ? (eam) + (a) byte (a) ? (ah) + (al) + (c) byte (a) ? (a) + (ear) + (c) byte (a) ? (a) + (eam) + (c) byte (a) ? (ah) + (al) + (c) (decimal) byte (a) ? (a) Cimm8 byte (a) ? (a) C (dir) byte (a) ? (a) C (ear) byte (a) ? (a) C (eam) byte (ear) ? (ear) C (a) byte (eam) ? (eam) C (a) byte (a) ? (ah) C (al) C (c) byte (a) ? (a) C (ear) C (c) byte (a) ? (a) C (eam) C (c) byte (a) ? (ah) C (al) C (c) (decimal) z z z z C z z z z z z z z z C C z z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C C * C C C C C C C C C * C C C C addw a addw a, ear addw a, eam addw a, #imm16 addw ear, a addw eam, a addcw a, ear addcw a, eam subw a subw a, ear subw a, eam subw a, #imm16 subw ear, a subw eam, a subcw a, ear subcw a, eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 0 0 (c) 0 0 2 (c) 0 (c) 0 0 (c) 0 0 2 (c) 0 (c) word (a) ? (ah) + (al) word (a) ? (a) +(ear) word (a) ? (a) +(eam) word (a) ? (a) +imm16 word (ear) ? (ear) + (a) word (eam) ? (eam) + (a) word (a) ? (a) + (ear) + (c) word (a) ? (a) + (eam) + (c) word (a) ? (ah) C (al) word (a) ? (a) C (ear) word (a) ? (a) C (eam) word (a) ? (a) Cimm16 word (ear) ? (ear) C (a) word (eam) ? (eam) C (a) word (a) ? (a) C (ear) C (c) word (a) ? (a) C (eam) C (c) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C C * C C C C C C C * C C addl a, ear addl a, eam addl a, #imm32 subl a, ear subl a, eam subl a, #imm32 2 2+ 5 2 2+ 5 6 7+ (a) 4 6 7+ (a) 4 2 0 0 2 0 0 0 (d) 0 0 (d) 0 long (a) ? (a) + (ear) long (a) ? (a) + (eam) long (a) ? (a) +imm32 long (a) ? (a) C (ear) long (a) ? (a) C (eam) long (a) ? (a) Cimm32 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C
108 mb90650a series table 10 increment and decrement instructions (byte/word/long word) [12 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 11 compare instructions (byte/word/long word) [11 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw inc ear inc eam dec ear dec eam 2 2+ 2 2+ 2 5+ (a) 3 5+ (a) 2 0 2 0 0 2 (b) 0 2 (b) byte (ear) ? (ear) +1 byte (eam) ? (eam) +1 byte (ear) ? (ear) C1 byte (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * incw ear incw eam decw ear decw eam 2 2+ 2 2+ 3 5+ (a) 3 5+ (a) 2 0 2 0 0 2 (c) 0 2 (c) word (ear) ? (ear) +1 word (eam) ? (eam) +1 word (ear) ? (ear) C1 word (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * incl ear incl eam decl ear decl eam 2 2+ 2 2+ 7 9+ (a) 7 9+ (a) 4 0 4 0 0 2 (d) 0 2 (d) long (ear) ? (ear) +1 long (eam) ? (eam) +1 long (ear) ? (ear) C1 long (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * mnemonic # ~ rg boperation lh ah i s t n z v c rmw cmp a cmp a, ear cmp a, eam cmp a, #imm8 1 2 2+ 2 1 2 3+ (a) 2 0 1 0 0 0 0 (b) 0 byte (ah) C (al) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? imm8 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpw a cmpw a, ear cmpw a, eam cmpw a, #imm16 1 2 2+ 3 1 2 3+ (a) 2 0 1 0 0 0 0 (c) 0 word (ah) C (al) word (a) ? (ear) word (a) ? (eam) word (a) ? imm16 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpl a, ear cmpl a, eam cmpl a, #imm32 2 2+ 5 6 7+ (a) 3 2 0 0 0 (d) 0 word (a) ? (ear) word (a) ? (eam) word (a) ? imm32 C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C
109 mb90650a series table 12 multiplication and division instructions (byte/word/long word) [11 instructions] *1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally. *2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally. *3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. *4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally. *5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. *6: (b) when the result is zero or when an overflow occurs, and 2 (b) normally. *7: (c) when the result is zero or when an overflow occurs, and 2 (c) normally. *8: 3 when byte (ah) is zero, and 7 when byte (ah) is not zero. *9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. *10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. *11: 3 when word (ah) is zero, and 11 when word (ah) is not zero. *12: 4 when word (ear) is zero, and 12 when word (ear) is not zero. *13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw divu a divu a, ear divu a, eam divuw a, ear divuw a, eam mulu a mulu a, ear mulu a, eam muluw a muluw a, ear muluw a, eam 1 2 2+ 2 2+ 1 2 2+ 1 2 2+ * 1 * 2 * 3 * 4 * 5 * 8 * 9 * 10 * 11 * 12 * 13 0 1 0 1 0 0 1 0 0 1 0 0 0 * 6 0 * 7 0 0 (b) 0 0 (c) word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (ear) byte (ah) *byte (al) ? word (a) byte (a) *byte (ear) ? word (a) byte (a) *byte (eam) ? word (a) word (ah) *word (al) ? long (a) word (a) *word (ear) ? long (a) word (a) *word (eam) ? long (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * C C C C C C * * * * * C C C C C C C C C C C C C C C C C
110 mb90650a series table 13 logical 1 instructions (byte/word) [39 instructions ] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw and a, #imm8 and a, ear and a, eam and ear, a and eam, a or a, #imm8 or a, ear or a, eam or ear, a or eam, a xor a, #imm8 xor a, ear xor a, eam xor ear, a xor eam, a not a not ear not eam 2 2 2+ 2 2+ 2 2 2+ 2 2+ 2 2 2+ 2 2+ 1 2 2+ 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 2 (b) byte (a) ? (a) and imm8 byte (a) ? (a) and (ear) byte (a) ? (a) and (eam) byte (ear) ? (ear) and (a) byte (eam) ? (eam) and (a) byte (a) ? (a) or imm8 byte (a) ? (a) or (ear) byte (a) ? (a) or (eam) byte (ear) ? (ear) or (a) byte (eam) ? (eam) or (a) byte (a) ? (a) xor imm8 byte (a) ? (a) xor (ear) byte (a) ? (a) xor (eam) byte (ear) ? (ear) xor (a) byte (eam) ? (eam) xor (a) byte (a) ? not (a) byte (ear) ? not (ear) byte (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C * C C C C * C C C C * C C * andw a andw a, #imm16 andw a, ear andw a, eam andw ear, a andw eam, a orw a orw a, #imm16 orw a, ear orw a, eam orw ear, a orw eam, a xorw a xorw a, #imm16 xorw a, ear xorw a, eam xorw ear, a xorw eam, a notw a notw ear notw eam 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 2 2+ 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 2 (c) word (a) ? (ah) and (a) word (a) ? (a) and imm16 word (a) ? (a) and (ear) word (a) ? (a) and (eam) word (ear) ? (ear) and (a) word (eam) ? (eam) and (a) word (a) ? (ah) or (a) word (a) ? (a) or imm16 word (a) ? (a) or (ear) word (a) ? (a) or (eam) word (ear) ? (ear) or (a) word (eam) ? (eam) or (a) word (a) ? (ah) xor (a) word (a) ? (a) xor imm16 word (a) ? (a) xor (ear) word (a) ? (a) xor (eam) word (ear) ? (ear) xor (a) word (eam) ? (eam) xor (a) word (a) ? not (a) word (ear) ? not (ear) word (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C C C C C * C C C C C * C C C C C * C C *
111 mb90650a series table 14 logical 2 instructions (long word) [6 instructions] table 15 sign inversion instructions (byte/word) [6 instructions] table 16 normalize instruction (long word) [1 instruction] *1: 4 when the contents of the accumulator are all zeroes, 6 + (r0) in all other cases (shift count). note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw andl a, ear andl a, eam orl a, ear orl a, eam xorl a, ea xorl a, eam 2 2+ 2 2+ 2 2+ 6 7+ (a) 6 7+ (a) 6 7+ (a) 2 0 2 0 2 0 0 (d) 0 (d) 0 (d) long (a) ? (a) and (ear) long (a) ? (a) and (eam) long (a) ? (a) or (ear) long (a) ? (a) or (eam) long (a) ? (a) xor (ear) long (a) ? (a) xor (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r r r r r r C C C C C C C C C C C C mnemonic # ~ rg boperation lh ah i s t n z v c rmw neg a neg ear neg eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 0 2 (b) byte (a) ? 0 C (a) byte (ear) ? 0 C (ear) byte (eam) ? 0 C (eam) x C C C C C C C C C C C C C C * * * * * * * * * * * * C C * negw a negw ear negw eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 0 2 (c) word (a) ? 0 C (a) word (ear) ? 0 C (ear) word (eam) ? 0 C (eam) C C C C C C C C C C C C C C C * * * * * * * * * * * * C C * mnemonic # ~ rg b operation lh ah i s t n z v c rmw nrml a, r0 2 * 1 1 0 long (a) ? shift until first digit is 1 byte (r0) ? current shift count CCCCCC*CC C
112 mb90650a series table 17 shift instructions (byte/word/long word) [18 instructions] *1: 6 when r0 is 0, 5 + (r0) in all other cases. *2: 6 when r0 is 0, 6 + (r0) in all other cases. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw rorc a rolc a rorc ear rorc eam rolc ear rolc eam asr a, r0 lsr a, r0 lsl a, r0 2 2 2 2+ 2 2+ 2 2 2 2 2 3 5+ (a) 3 5+ (a) * 1 * 1 * 1 0 0 2 0 2 0 1 1 1 0 0 0 2 (b) 0 2 (b) 0 0 0 byte (a) ? right rotation with carry byte (a) ? left rotation with carry byte (ear) ? right rotation with carry byte (eam) ? right rotation with carry byte (ear) ? left rotation with carry byte (eam) ? left rotation with carry byte (a) ? arithmetic right barrel shift (a, r0) byte (a) ? logical right barrel shift (a, r0) byte (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * * * * * * * * * * * * * * * * * C C C C C C C C C * * * * * * * * * C C C * C * C C C asrw a lsrw a/shrw a lslw a/shlw a asrw a, r0 lsrw a, r0 lslw a, r0 1 1 1 2 2 2 2 2 2 * 1 * 1 * 1 0 0 0 1 1 1 0 0 0 0 0 0 word (a) ? arithmetic right shift (a, 1 bit) word (a) ? logical right shift (a, 1 bit) word (a) ? logical left shift (a, 1 bit) word (a) ? arithmetic right barrel shift (a, r0) word (a) ? logical right barrel shift (a, r0) word (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * r * * * * * * * * * * C C C C C C * * * * * * C C C C C C asrl a, r0 lsrl a, r0 lsll a, r0 2 2 2 * 2 * 2 * 2 1 1 1 0 0 0 long (a) ? arithmetic right shift (a, r0) long (a) ? logical right barrel shift (a, r0) long (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C * * C * * * * * * C C C * * * C C C
113 mb90650a series table 18 branch 1 instructions [31 instructions] *1: 4 when branching, 3 when not branching. *2: (b) + 3 (c) *3: read (word) branch address. *4: w: save (word) to stack; r: read (word) branch address. *5: save (word) to stack. *6: w: save (long word) to w stack; r: read (long word) r branch address. *7: save (long word) to stack. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel bra rel jmp @a jmp addr16 jmp @ear jmp @eam jmpp @ear * 3 jmpp @eam * 3 jmpp addr24 call @ear * 4 call @eam * 4 call addr16 * 5 callv #vct4 * 5 callp @ear * 6 callp @eam * 6 callp addr24 * 7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 2+ 4 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10 11+ (a) 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2 (c) (c) 2 (c) 2 (c) * 2 2 (c) branch when (z) = 1 branch when (z) = 0 branch when (c) = 1 branch when (c) = 0 branch when (n) = 1 branch when (n) = 0 branch when (v) = 1 branch when (v) = 0 branch when (t) = 1 branch when (t) = 0 branch when (v) xor (n) = 1 branch when (v) xor (n) = 0 branch when ((v) xor (n)) or (z) = 1 branch when ((v) xor (n)) or (z) = 0 branch when (c) or (z) = 1 branch when (c) or (z) = 0 branch unconditionally word (pc) ? (a) word (pc) ? addr16 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? (ear), (pcb) ? (ear +2) word (pc) ? (eam), (pcb) ? (eam +2) word (pc) ? ad24 0 to 15, (pcb) ? ad24 16 to 23 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? addr16 vector call instruction word (pc) ? (ear) 0 to 15, (pcb) ? (ear) 16 to 23 word (pc) ? (eam) 0 to 15, (pcb) ? (eam) 16 to 23 word (pc) ? addr0 to 15, (pcb) ? addr16 to 23 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
114 mb90650a series table 19 branch 2 instructions [19 instructions] *1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: retrieve (word) from stack *8: retrieve (long word) from stack *9: in the cbne/cwbne instruction, do not use the rwj+ addressing mode. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw cbne a, #imm8, rel cwbne a, #imm16, rel cbne ear, #imm8, rel cbne eam, #imm8, rel* 9 cwbne ear, #imm16, rel cwbne eam, #imm16, rel* 9 dbnz ear, rel dbnz eam, rel dwbnz ear, rel dwbnz eam, rel int #vct8 int addr16 intp addr24 int9 reti link #local8 unlink ret * 7 retp * 8 3 4 4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2 1 1 1 * 1 * 1 * 2 * 3 * 4 * 3 * 5 * 6 * 5 * 6 20 16 17 20 15 6 5 4 6 0 0 1 0 1 0 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 (b) 0 (c) 0 2 (b) 0 2 (c) 8 (c) 6 (c) 6 (c) 8 (c) 6 (c) (c) (c) (c) (d) branch when byte (a) 1 imm8 branch when word (a) 1 imm16 branch when byte (ear) 1 imm8 branch when byte (eam) 1 imm8 branch when word (ear) 1 imm16 branch when word (eam) 1 imm16 branch when byte (ear) = (ear) C 1, and (ear) 1 0 branch when byte (eam) = (eam) C 1, and (eam) 1 0 branch when word (ear) = (ear) C 1, and (ear) 1 0 branch when word (eam) = (eam) C 1, and (eam) 1 0 software interrupt software interrupt software interrupt software interrupt return from interrupt at constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area at constant entry, retrieve old frame pointer from stack. return from subroutine return from subroutine C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r r r r * C C C C C C C C C C C C C C s s s s * C C C C C C C C C C C C C C C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * C C C C C C C C * C C C C C C C C C C C * C * C C C C C C C C C
115 mb90650a series table 20 other control instructions (byte/word/long word) [36 instructions] *1: pcb, adb, ssb, usb, and spb : 1 state dtb, dpr : 2 states *2: 7 + 3 (pop count) + 2 (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) C 3 (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: pop count (c), or push count (c) *5: pop count or push count. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw pushw a pushw ah pushw ps pushw rlst popw a popw ah popw ps popw rlst jctx @a and ccr, #imm8 or ccr, #imm8 mov rp, #imm8 mov ilm, #imm8 movea rwi, ear movea rwi, eam movea a, ear movea a, eam addsp #imm8 addsp #imm16 mov a, brgl mov brg2, a nop adb dtb pcb spb ncc cmr 1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 1 1 1 1 1 1 1 4 4 4 * 3 3 3 4 * 2 14 3 3 2 2 3 2+ (a) 1 1+ (a) 3 3 * 1 1 1 1 1 1 1 1 1 0 0 0 * 5 0 0 0 * 5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) (c) (c) * 4 (c) (c) (c) * 4 6 (c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word (sp) ? (sp) C2, ((sp)) ? (a) word (sp) ? (sp) C2, ((sp)) ? (ah) word (sp) ? (sp) C2, ((sp)) ? (ps) (sp) ? (sp) C2n, ((sp)) ? (rlst) word (a) ? ((sp)), (sp) ? ( sp) +2 word (ah) ? ((sp)), (sp) ? ( sp) +2 word (ps) ? ((sp)), (sp) ? ( sp) +2 (rlst) ? ((sp)), (sp) ? (sp) +2n context switch instruction byte (ccr) ? (ccr) and imm8 byte (ccr) ? (ccr) or imm8 byte (rp) ? imm8 byte (ilm) ? imm8 word (rwi) ? ear word (rwi) ? eam word(a) ? ear word (a) ? eam word (sp) ? (sp) +ext (imm8) word (sp) ? (sp) +imm16 byte (a) ? (brgl) byte (brg2) ? (a) no operation prefix code for accessing ad space prefix code for accessing dt space prefix code for accessing pc space prefix code for accessing sp space prefix code for no flag change prefix code for common register bank C C C C C C C C C C C C C C C C C C C z C C C C C C C C C C C C * C C C C C C C C C C * * C C * C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * C C C C C C C C C C C C C * C * * * C C C C C C C C * * C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
116 mb90650a series table 21 bit manipulation instructions [21 instructions] *1: 8 when branching, 7 when not branching *2: 7 when branching, 6 when not branching *3: 10 when condition is satisfied, 9 when not satisfied *4: undefined count *5: until condition is satisfied note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw movb a, dir:bp movb a, addr16:bp movb a, io:bp movb dir:bp, a movb addr16:bp, a movb io:bp, a setb dir:bp setb addr16:bp setb io:bp clrb dir:bp clrb addr16:bp clrb io:bp bbc dir:bp, rel bbc addr16:bp, rel bbc io:bp, rel bbs dir:bp, rel bbs addr16:bp, rel bbs io:bp, rel sbbs addr16:bp, rel wbts io:bp wbtc io:bp 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 5 5 4 7 7 6 7 7 7 7 7 7 * 1 * 1 * 2 * 1 * 1 * 2 * 3 * 4 * 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (b) (b) (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) (b) (b) (b) (b) (b) (b) 2 (b) * 5 * 5 byte (a) ? (dir:bp) b byte (a) ? (addr16:bp) b byte (a) ? (io:bp) b bit (dir:bp) b ? (a) bit (addr16:bp) b ? (a) bit (io:bp) b ? (a) bit (dir:bp) b ? 1 bit (addr16:bp) b ? 1 bit (io:bp) b ? 1 bit (dir:bp) b ? 0 bit (addr16:bp) b ? 0 bit (io:bp) b ? 0 branch when (dir:bp) b = 0 branch when (addr16:bp) b = 0 branch when (io:bp) b = 0 branch when (dir:bp) b = 1 branch when (addr16:bp) b = 1 branch when (io:bp) b = 1 branch when (addr16:bp) b = 1, bit = 1 wait until (io:bp) b = 1 wait until (io:bp) b = 0 z z z C C C C C C C C C C C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * C C C C C C C C C C C C C C C * * * * * * C C C C C C * * * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * C C C C C C * C C
117 mb90650a series table 22 accumulator manipulation instructions (byte/word) [6 instructions] table 23 string instructions [10 instructions] m: rw0 value (counter value) n: loop count *1: 5 when rw0 is 0, 4 + 7 (rw0) for count out, and 7 n + 5 when match occurs *2: 5 when rw0 is 0, 4 + 8 (rw0) in any other case *3: (b) (rw0) + (b) (rw0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) n *5: 2 (rw0) *6: (c) (rw0) + (c) (rw0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) n *8: 2 (rw0) note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw swap swapw ext extw zext zextw 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 byte (a) 0 to 7 ? (a) 8 to 15 word (ah) ? (al) byte sign extension word sign extension byte zero extension word zero extension C C x C z C C * C x C z C C C C C C C C C C C C C C C C C C C C * * r r C C * * * * C C C C C C C C C C C C C C C C C C mnemonic # ~ rg b operation lh ah i s t n z v c rmw movs/movsi movsd sceq/sceqi sceqd fisl/filsi 2 2 2 2 2 * 2 * 2 * 1 * 1 6m +6 * 5 * 5 * 5 * 5 * 5 * 3 * 3 * 4 * 4 * 3 byte transfer @ah+ ? @al+, counter = rw0 byte transfer @ahC ? @alC, counter = rw0 byte retrieval (@ah+) C al, counter = rw0 byte retrieval (@ahC) C al, counter = rw0 byte filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C movsw/movswi movswd scweq/scweqi scweqd filsw/filswi 2 2 2 2 2 * 2 * 2 * 1 * 1 6m +6 * 8 * 8 * 8 * 8 * 8 * 6 * 6 * 7 * 7 * 6 word transfer @ah+ ? @al+, counter = rw0 word transfer @ahC ? @alC, counter = rw0 word retrieval (@ah+) C al, counter = rw0 word retrieval (@ahC) C al, counter = rw0 word filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C
118 mb90650a series n ordering information model package remarks mb90652apfv MB90653Apfv mb90p653apfv mb90654apfv mb90f654apfv 100-pin plastic lqfp (fpt-100p-m05) mb90652apf MB90653Apf mb90p653apf mb90654apf mb90f654apf 100-pin plastic qfp (fpt-100p-m06)
119 mb90650a series n package dimensions c 1995 fujitsu limited f100007s-2c-3 details of "b" part 16.00?.20(.630?008)sq 14.00?.10(.551?004)sq 0.50(.0197)typ .007 ?001 +.003 ?.03 +0.08 0.18 index 0.10(.004) 0.08(.003) m .059 ?004 +.008 ?.10 +0.20 1.50 .005 ?001 +.002 ?.02 +0.05 0.127 15.00 12.00 (.472) ref (.591) nom "b" "a" 25 26 1 100 75 51 50 76 0.50?.20(.020?008) details of "a" part 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 0.10?.10 (.004?004) (stand off) 0~10 lead no. (mouting height) c 1994 fujitsu limited f100008-3c-2 "a" "b" 0.10(.004) 0.53(.021)max 0.18(.007)max details of "a" part 0 10 details of "b" part 12.35(.486) ref 16.30?.40 (.642?016) 0.05(.002)min (stand off) 0.15?.05(.006?002) index 23.90?.40(.941?016) 20.00?.20(.787?008) 17.90?.40 14.00?.20 (.551?008) (.705?016) 0.13(.005) m 18.85(.742)ref 22.30?.40(.878?016) 1 30 31 50 51 80 81 100 0.25(.010) 0.30(.012) 0.65(.0256)typ 0.30?.10 (.012?004) lead no. 0.80?.20 (.031?008) 3.35(.132)max (mounting height) 100-pin plastic lqfp (fpt-100p-m05) 100-pin plastic qfp (fpt-100p-m06) dimensions in mm (inches) dimensions in mm (inches)
mb90650a series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9910 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

▲Up To Search▲

Price & Availability of MB90653A

	To Download MB90653A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .